DRAM ECC Partial Write Coalescing via Threshold Tracking

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Solution Overview

Problem

The existing method of managing writes from a Level 2 cache to DRAM in ECC mode results in significant latency and memory bandwidth consumption due to the need for fill requests to ensure full 32-byte data transfers for ECC checksum calculation, especially with partial writes.

Innovation Solution

Implement a method to track partial writes in the data cache and issue fill requests only when the number of partial writes exceeds a predetermined threshold, allowing partial writes to coalesce and avoid unnecessary fill requests, thereby reducing latency and bandwidth usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If fill requests are issued for every partial write to ensure full 32-byte data transfers for ECC checksum calculation, then data integrity and ECC functionality are maintained, but memory latency and bandwidth consumption increase significantly

Engineering Contradiction:
Improvedata integrityVSAvoidmemory latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary tracking of partial write counts in the L2 cache before issuing fill requests. By monitoring the number of partial writes and comparing against a threshold, the system determines whether a fill request is necessary, thereby avoiding premature or unnecessary fill operations that would increase latency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Instead of issuing fill requests for every partial write (excessive action), the system applies partial action by only issuing fill requests when the partial write count exceeds a predetermined threshold. This selective approach maintains ECC functionality when needed while reducing unnecessary memory operations.

Inventive Principle:
Principle #16Partial or excessive action

2Reliability

If fill requests are issued for every partial write to ensure full 32-byte data transfers, then ECC checksum calculation can be performed, but memory bandwidth consumption increases

Engineering Contradiction:
ImproveECC functionalityVSAvoidmemory bandwidth consumption
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The system performs preliminary tracking of partial write counts in the L2 cache before issuing fill requests. By monitoring the number of partial writes and comparing against a threshold, the system determines whether a fill request is necessary, thereby avoiding premature or unnecessary fill operations that would consume bandwidth.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Instead of issuing fill requests for every partial write (excessive action), the system applies partial action by only issuing fill requests when the partial write count exceeds a predetermined threshold. This selective approach maintains ECC functionality when needed while reducing unnecessary memory operations.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If the L2 cache ensures all dirty data is fully covered for ECC checksum computation, then data reliability is improved, but system performance deteriorates due to frequent fill requests

Engineering Contradiction:
Improvedata reliabilityVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system performs preliminary tracking of partial write counts in the L2 cache before issuing fill requests. By monitoring the number of partial writes and comparing against a threshold, the system determines whether a fill request is necessary, thereby avoiding premature or unnecessary fill operations that would reduce performance.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Instead of issuing fill requests for every partial write (excessive action), the system applies partial action by only issuing fill requests when the partial write count exceeds a predetermined threshold. This selective approach maintains ECC functionality when needed while reducing unnecessary memory operations.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9110809B2Reducing memory traffic in DRAM ECC mode
Publication Date: 2015.08.18 NVIDIA CORP
  • US9110809B2 patent drawing
  • US9110809B2 patent drawing
  • US9110809B2 patent drawing

AI summary

A method for managing memory traffic includes causing first data to be written to a data cache memory, where a first write request comprises a partial write and writes the first data to a first portion of the data cache memory, and further includes tracking the number of partial writes in the data cache memory. The method further includes issuing a fill request for one or more partial writes in the data cache memory if the number of partial writes in the data cache memory is greater than a predetermined first threshold.