ECC Circuit Read-Write Path Separation for Timing Margin
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in managing the timing of error correction code (ECC) circuit operations when logic components are shared for both write and read operations, leading to difficulties in maintaining timing margins.
Innovation Solution
The ECC circuit includes a shared logic tree for both write and read operations, with separate read and write paths, where the read parity bit is decoupled from the logic tree, allowing the generation of encoded bits to be separated from comparing them to read parity bits, thereby increasing timing margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a shared logic tree is used for both write and read operations, then device complexity is reduced, but timing margin is compromised
Solution Approach 1:
The ECC circuit is segmented into separate write path and read path, with the logic tree dedicated to write operations and a separate syndrome generator for read operations. This segmentation allows each path to be optimized independently for its specific timing requirements, resolving the conflict between shared resource complexity reduction and timing margin maintenance.
Solution Approach 2:
The syndrome generation function is extracted from the write path and placed in a separate read path. This extraction allows the syndrome generator to operate independently with its own timing, preventing timing conflicts with write operations while maintaining the benefits of functional separation.
2Loss of time
If read parity bits are held in the read path, then timing margin is improved, but device complexity increases
Solution Approach 1:
The read path is designed to handle multiple functions including holding read parity bits, generating syndromes, and performing error correction. By making the read path multi-functional, the design achieves improved timing margins without proportionally increasing overall device complexity, as the same infrastructure serves multiple purposes.
Data Source
AI summary
Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. A first latch may hold the encoded bit and provide it as a write parity bit to the memory array as part of a write operation. A second latch may hold a parity bit read from the memory array and the ECC circuit may generate a command signal based on that parity bit. A multiplexer latch may hold the encoded bit and provide a syndrome bit based on the command signal and the encoded bit. The syndrome bit may indicate if there is mismatch between the parity bit and the encoded bit. The logic which handles generating the syndrome bit may be separated from the logic tree.