ECC Architecture Prioritized Task Queues for Decoding Latency
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Solution Overview
Problem
In multi-level and multi-round error control schemes, existing ECC architectures face increased decoding latency due to higher bit error rates, which necessitate a reduction in processing time for error recovery.
Innovation Solution
An ECC architecture with multiple task queues is implemented, where tasks are assigned different priorities, and re-decoding tasks are escalated in priority to ensure faster execution, reducing latency by prioritizing re-decoding tasks over normal tasks in a multi-channel NAND storage system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple levels of decoding and multiple rounds of data retrieval are performed to handle higher bit error rates, then error recovery capability is improved, but decoding latency increases
Solution Approach 1:
The system dynamically adjusts task priority levels based on decoding round number. Re-decoding tasks automatically escalate to higher priority levels (e.g., from normal priority to high priority) upon failure, enabling adaptive response to decoding failures without static configuration. This dynamic priority adjustment resolves the contradiction by allowing flexible time allocation - critical re-decoding operations receive immediate attention while initial decoding maintains normal flow.
Solution Approach 2:
The task queue is segmented into multiple priority levels (e.g., high priority and normal priority queues). Re-decoding tasks are routed to separate high-priority queues, creating distinct processing paths. This segmentation allows the system to handle time-critical re-decoding operations separately from routine decoding, reducing overall latency while maintaining comprehensive error recovery capability across multiple decoding levels.
2Device complexity
If re-decoding tasks are mixed with first-decoding tasks in the same queue, then queue management is simplified, but processing speed of re-decoding tasks decreases
Solution Approach 1:
The system divides the single task queue into multiple priority-based queues (e.g., high priority queue for re-decoding tasks, normal priority queue for first-decoding tasks). This segmentation creates fast processing paths for time-critical re-decoding operations while maintaining organized queue management through clear priority distinctions. The arbitration rule automatically directs high-priority re-decoding tasks to dedicated queues, ensuring rapid processing without complex manual intervention.
Solution Approach 2:
The system changes the priority parameter of tasks based on their decoding round status. When a decoding task fails, its priority level is escalated (e.g., from level 0 to level 1), transforming it from a normal decoding task to a high-priority re-decoding task. This parameter change enables automatic differentiation between task types without requiring separate queue management logic, resolving the speed-complexity contradiction through dynamic parameter adjustment.
3Measurement precision
If higher bit error rates are handled through multiple decoding levels, then data accuracy is improved, but processing time increases
Solution Approach 1:
The system implements dynamic priority escalation where re-decoding tasks automatically transition to higher priority levels upon decoding failure. This dynamic adjustment ensures that time-critical re-decoding operations receive immediate processing resources, reducing the duration of action for error recovery while maintaining multiple decoding levels for data accuracy. The system adapts processing time allocation based on actual decoding needs rather than using fixed time schedules.
Data Source
AI summary
Systems, apparatus and methods are provided for an error correction code (ECC) architecture with reduced decoding latency in error control. An apparatus may comprise control circuitry configured to receive a status report that a decoding task has failed, determine that a higher priority is needed for a re-decoding task, generate a NAND read task having a second priority level higher than a first priority level of the failed decoding task, and generate an ECC re-decoding task having the second priority level.