ECC Proxy Bridge for Multi-Master SoC Data Integrity
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Solution Overview
Problem
Multi-master systems in system-on-chip (SoC) designs often lack error correction code (ECC) support, particularly in non-ECC memory devices, which hinders effective data integrity and reliability due to architectural and cost constraints.
Innovation Solution
The implementation of an ECC proxy bridge with hardened circuitry in the SoC, which establishes an ECC proxy region in memory and calculates and inserts ECC bytes into write transactions, enabling error correction functionality even in non-ECC memory systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC memory is used to provide error correction functionality, then data integrity is improved, but device complexity and cost increase due to additional ICs and real estate requirements
Solution Approach 1:
The patent introduces an ECC proxy bridge as an intermediary component between non-ECC memory and master circuits. This bridge calculates and inserts ECC bytes into write transactions and verifies ECC on read transactions, providing error correction functionality without requiring the memory itself to be ECC-capable. The proxy bridge acts as a mediator that adds ECC functionality to the memory subsystem without changing the fundamental non-ECC nature of the memory device.
Solution Approach 2:
The ECC proxy bridge implements ECC functionality as a separate copy or duplicate of the error correction logic, rather than integrating it directly into the memory device. This allows the ECC functionality to be provided through a standalone component that can serve multiple memory channels or masters, reducing the overall complexity compared to having ECC capability built into each memory device.
2Reliability
If ECC functionality is added to non-ECC memory devices, then data integrity is improved, but area increases due to additional ICs and real estate on the memory module
Solution Approach 1:
The ECC proxy bridge merges multiple functions into a single component: ECC calculation, ECC insertion into write transactions, ECC verification on read transactions, and memory address tagging. By combining these functions that would otherwise require separate components, the design reduces the total area required compared to having separate ECC ICs and other components.
Solution Approach 2:
The ECC proxy bridge is designed as a universal component that can serve multiple masters and handle multiple memory channels simultaneously. The bridge can process ECC for different memory regions and support multiple independent memory interfaces, providing multi-functionality that reduces the need for separate ECC implementations for each memory channel or master.
3Productivity
If hardened circuitry is used in the ECC proxy bridge, then system performance is improved, but device complexity increases
Solution Approach 1:
The ECC proxy bridge is segmented into distinct functional blocks: write path logic for ECC calculation and insertion, read path logic for ECC verification, address tagging logic, and control logic. Each segment handles a specific aspect of ECC functionality, allowing for optimized performance in each function while keeping the overall design manageable through clear separation of concerns.
Solution Approach 2:
The ECC proxy bridge performs self-service by automatically calculating ECC bytes and inserting them into write transactions without external intervention. The bridge also autonomously verifies ECC on read transactions and handles error correction decisions, reducing the need for external control logic and simplifying the overall system architecture despite the complexity of the hardened circuitry.
Data Source
AI summary
An example multi-master system in a system-on-chip (SoC) includes a plurality of master circuits, an error-correcting code (ECC) proxy bridge comprising hardened circuitry in the SoC, a local interconnect configured to couple the plurality of master circuits to the ECC proxy bridge, a memory not having ECC support, and a system interconnect configured to couple the ECC proxy bridge to the memory. The ECC proxy bridge is configured to establish an ECC proxy region in the memory and, for each write transaction from the plurality of master circuits that targets the ECC proxy region, calculate and insert ECC bytes into the respective write transaction.