ECC Proxy Circuit for Interconnect Error Correction in SoC
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Solution Overview
Problem
In System-on-a-Chip (SoC) applications, errors introduced in interconnect circuitry between a bus master circuit and memory are not effectively remedied by existing error-correcting mechanisms, as these mechanisms are typically implemented within the memory controller and do not cover errors in the interconnect circuitry.
Innovation Solution
An Error Correction Code (ECC) proxy circuit is deployed between interconnects to generate and transmit ECCs for write transactions and supplement read transactions with ECC references, providing error detection and correction capabilities without the need for local ECC on the memory controller, thus covering errors in the interconnect circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error-correcting mechanisms are implemented within the memory controller, then data integrity in memory is improved, but errors in interconnect circuitry remain uncovered
Solution Approach 1:
An ECC proxy circuit is introduced as an intermediary component between the bus master circuit and the memory. This proxy circuit receives transactions from the bus master, generates or retrieves ECC codes, and forwards them to the memory, thereby extending error correction coverage from just memory to include the interconnect circuitry without modifying the memory controller's internal structure
2Reliability
If ECC proxy circuit is deployed between interconnects, then error detection and correction in interconnects is enabled, but device complexity increases
Solution Approach 1:
The ECC proxy circuit is designed to handle multiple functions: it processes both read transactions (by retrieving ECC codes from memory) and write transactions (by generating and storing ECC codes). This multi-functionality reduces the need for separate dedicated circuits for each operation, thereby limiting the increase in device complexity while achieving comprehensive error correction
3Reliability
If ECC codes are generated and transmitted for all write transactions, then error correction capability is improved, but data transmission overhead increases
Solution Approach 1:
ECC codes are generated in advance during write transactions and stored in the memory at designated locations. This preliminary action allows the ECC codes to be readily available when read transactions occur, eliminating the need to re-transmit or re-generate them, thereby reducing redundant data transmission and minimizing overhead
Data Source
AI summary
In approaches for correction of errors introduced in an interconnect circuit, an ECC proxy circuit is coupled between a first interconnect and the second interconnect, and generates for each of the write transactions from a bus master circuit, a first ECC from and associated with data of the write transaction, and transmits the write transaction and associated first ECC on the second interconnect. The ECC proxy circuit also supplements each of the read transactions from the bus master circuit with a reference to a second ECC associated with data referenced by the read transaction. The ECC proxy circuit transmits the read transaction that references the second ECC on the second interconnect. At least one random access memory (RAM) is coupled to the ECC proxy circuit through the second interconnect. The RAM stores data of each write transaction and the first ECC.