ECC-RAID Joint Decoding for Undecodable Memory Codewords

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Solution Overview

Problem

Data storage devices face challenges in maintaining storage density due to increased bit error rates and the need for additional protection against memory defects and failures, which requires memory overprovisioning for error correction coding (ECC) and redundant array of independent disks (RAID) parity, limiting efficiency.

Innovation Solution

Implementing joint ECC and RAID decoding to efficiently utilize overprovisioning, leveraging unused RAID capacity for random error correction when no memory defects occur or when defects are less than the RAID correction capability, by exchanging information between ECC and RAID decoders to enhance error correction capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If more parity bits are used to increase error correction capacity, then error correction capability is improved, but storage density deteriorates

Engineering Contradiction:
Improveerror correction capabilityVSAvoidstorage density
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent combines ECC decoding and RAID decoding into a unified joint decoding process. The ECC decoder and RAID decoder share common components including the same-parity-check decoder, syndrome calculator, and iterative decoding mechanism. This merging allows the system to achieve both ECC error correction capability and RAID fault tolerance using a single integrated decoder structure, effectively utilizing the parity bits for dual purposes without requiring separate dedicated storage for each protection mechanism.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If memory overprovisioning is increased to store ECC and RAID parity, then data protection is improved, but storage efficiency deteriorates

Engineering Contradiction:
Improvedata protectionVSAvoidstorage efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The joint decoder is designed to perform multiple functions: it can decode ECC codewords independently, decode RAID stripes independently, and perform joint ECC-RAID decoding when both protections are applicable. The same-parity-check decoder can function as either an ECC syndrome calculator or a RAID parity checker depending on the decoding mode. This multi-functionality allows the system to maximize the utilization of overprovisioned memory space for storing parity information that serves dual protection purposes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system dynamically adjusts decoding parameters and strategies based on the specific error or failure condition detected. When random errors are detected, the decoder operates in ECC mode with specific syndrome calculation and error correction parameters. When memory defects are detected, it switches to RAID mode with different parity reconstruction parameters. This parameter adaptation allows optimal use of the available parity bits for the specific protection scenario, improving storage efficiency.

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If separate ECC and RAID decoding is performed, then decoding simplicity is maintained, but correction efficiency deteriorates

Engineering Contradiction:
Improvedecoding simplicityVSAvoidcorrection efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent merges ECC decoding and RAID decoding operations into a single joint decoding process that shares computational resources. The same-parity-check decoder is used for both ECC syndrome calculation and RAID parity verification. The iterative decoding algorithm combines ECC belief propagation with RAID XOR operations in a unified framework, reducing the total number of decoding passes required compared to separate independent decoding processes.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9940194B2ECC decoding using raid-type parity
Publication Date: 2018.04.10 SANDISK TECHNOLOGIES LLC
  • US9940194B2 patent drawing
  • US9940194B2 patent drawing
  • US9940194B2 patent drawing

AI summary

A device includes a memory and a controller. The controller is configured to read codewords of a data structure from the memory. The codewords include a number of undecodable codewords that are undecodable at an error correction coding (ECC) decoder according to a first correction scheme. The data structure further includes stripe parity corresponding to portions of the codewords encoded according to a stripe correction scheme. The controller is configured, in response to the number of the undecodable codewords exceeding an erasure correction capacity of the stripe correction scheme, to provide information from a stripe decoding operation to an input of a ECC decoding operation corresponding to an undecodable codeword.