ECC Decoder Reliability Mapping for Multi-Level Cell Memory
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Solution Overview
Problem
Nonvolatile memory devices with multi-level cells face challenges in maintaining high error correction capabilities due to increased degeneration and decreased operation speeds, particularly in reading data from multi-level cells where the number of states programmed increases, leading to reduced error correction efficiency.
Innovation Solution
An ECC decoder system that includes a buffer, a data converter, and a decoding circuit, which adjusts reliability parameters of read bits based on state-bit mapping information to generate ECC input data, and performs initial and re-decoding operations to correct errors, thereby enhancing error correction probability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cell scheme is used to increase memory capacity, then memory capacity increases, but error correction capability deteriorates
Solution Approach 1:
The patent segments the reading process into multiple phases: initial reading, reliability parameter adjustment, and re-decoding. By dividing the error correction process into distinct stages with different reliability parameters, the system can optimize correction for each phase while maintaining high memory capacity through MLC architecture.
Solution Approach 2:
The patent dynamically adjusts reliability parameters based on the decoding phase. The system transitions from using first reliability parameters during initial reading to second reliability parameters during re-decoding of uncorrected pages, allowing adaptive optimization of error correction capability without reducing memory capacity.
2Quantity of substance
If multi-level cell scheme is used to increase memory capacity, then memory capacity increases, but operation speed decreases
Solution Approach 1:
The patent implements periodic action by performing initial decoding on all pages, then selectively re-decoding only the uncorrected pages with adjusted reliability parameters. This periodic two-phase approach maintains high operation speed by avoiding redundant re-decoding of already corrected pages while ensuring thorough error correction.
Solution Approach 2:
The patent applies local quality by using different reliability parameters for different decoding scenarios: first reliability parameters for initial reading and second reliability parameters specifically for re-decoding uncorrected pages. This localized parameter adjustment optimizes operation speed by applying enhanced correction only where needed.
3Reliability
If re-decoding operation is performed on uncorrected pages, then error correction probability increases, but processing time increases
Solution Approach 1:
The patent applies partial action by performing re-decoding operations only on uncorrected pages rather than all pages. This selective approach increases error correction probability for problematic pages while minimizing processing time by avoiding redundant operations on already corrected pages.
Solution Approach 2:
The patent uses feedback from the initial decoding results to guide subsequent re-decoding operations. The system identifies uncorrected pages based on initial decoding outcomes and applies adjusted reliability parameters specifically to those pages, creating a feedback loop that optimizes error correction probability while controlling processing time.
Data Source
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AI summary
Described is an error check code (ECC) decoder which includes a buffer, a data converter and a decoding circuit. The buffer stores a plurality of read pages read from a plurality of multi-level cells connected to a same wordline. The data converter adjusts reliability parameters of read bits of the plurality of read pages based on state-bit mapping information and the plurality of read pages to generate a plurality of ECC input data respectively corresponding to the plurality of read pages. The state-bit mapping information indicate mapping relationships between states and bits stored in the plurality of multi-level cells. The decoding circuit performs an ECC decoding operation with respect to the plurality of read pages based on the plurality of ECC input data. An error correction probability is increased by adjusting the reliability parameters of read bits based on the state-bit mapping information.