Memory Controller ECC Retry Flow via Read Data Buffer

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Solution Overview

Problem

Existing memory systems with error checking and correction (ECC) face significant delays due to the need for inline correction or separate detection and correction paths, especially when errors occur, leading to thousands of clock cycles of latency.

Innovation Solution

Implementing a retry flow that utilizes a read data buffer (RDB) to store read data, allowing for fast ECC error correction by accessing the buffered data instead of re-reading from memory, thereby reducing latency and overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If inline correction is used for all read data, then error correction capability is improved, but data processing time increases due to passing through error correction logic for all reads

Engineering Contradiction:
Improveerror correction capabilityVSAvoiddata processing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the ECC correction process into two paths: a fast inline correction path for single errors and a slower server ECC path for multiple or uncorrectable errors. This allows the system to use simple, fast correction for most reads while reserving complex correction for only when necessary, resolving the contradiction between reliability and time loss.

Inventive Principle:
Principle #1Segmentation

2Speed

If separate detection and correction paths are used, then data processing speed for error-free reads is improved, but correction time for erroneous reads increases significantly

Engineering Contradiction:
Improvedata processing speedVSAvoidcorrection time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent performs preliminary error detection on all read data using a fast detection path. When errors are detected, the system prepares corrected data in advance using the read data buffer, so that when the slow server ECC correction is needed, the corrected data is already ready or can be quickly generated without restarting the entire read operation, thus reducing the time penalty for erroneous reads.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If traffic is stopped for error correction retry flow, then correction accuracy is improved, but system productivity decreases due to thousands of clock cycles delay

Engineering Contradiction:
Improvecorrection accuracyVSAvoidsystem productivity
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent introduces a read data buffer as an intermediary storage that holds read data temporarily. When errors are detected, instead of stopping traffic and retrying from memory, the system uses the buffer to quickly retrieve the read data for correction, eliminating the need to halt the entire memory traffic stream and thus maintaining high system productivity while ensuring accurate correction.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Reliability

If read data is reread from memory for correction, then correction reliability is improved, but time consumption increases due to additional read operations

Engineering Contradiction:
Improvecorrection reliabilityVSAvoidtime consumption
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary action by storing read data in the read data buffer immediately after the initial read operation. When errors are later detected, the system retrieves the data from the buffer rather than rereading from memory, significantly reducing the time consumption while maintaining correction reliability since the same data is used for correction.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12242342B2Fast memory ECC error correction
Publication Date: 2025.03.04 SK HYNIX NAND PRODUCT SOLUTIONS CORP
  • US12242342B2 patent drawing
  • US12242342B2 patent drawing
  • US12242342B2 patent drawing

AI summary

A memory controller having an error checking and correction (ECC) circuitry can detect an error in data being read from memory and correct that error with a retry flow without needing to send another read to the memory for the data. The read data is stored in a read data buffer (RDB) at the memory controller when the read data is received from memory. The memory controller has an error detection path from the RDB to the host and an error correction path. Read data that has no errors can be sent directly to the host. Instead of flushing the RDB in response to the error detection, the memory controller executes a retry flow, where the RDB provides the read data to the error correction path for error correction.