ECC Scrub Scheme Parity Bit Correction

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Solution Overview

Problem

Existing error correcting code (ECC) schemes in memory devices require significant storage space and consume time and power due to the need for encoding and decoding processes, especially during scrub operations, which can lead to increased power consumption and longer operation times.

Innovation Solution

The proposed solution involves an ECC scrub scheme that corrects errors associated with parity bits in memory arrays, allowing for the omission of encoding processes in certain circumstances, thereby reducing storage space and power consumption, and improving operation timing by directly writing corrected parity bits to the memory array without additional encoding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional ECC encoding and decoding processes are used during scrub operations, then error correction capability is maintained, but power consumption increases and operation time lengthens

Engineering Contradiction:
Improveerror correction capabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent extracts and eliminates the encoding process from the ECC scrub operation, keeping only the decoding and correction functions. This removes unnecessary computational steps while preserving the essential error correction capability, thereby reducing power consumption without sacrificing reliability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs preliminary encoding of data bits and parity bits before they are stored in the memory array. During subsequent scrub operations, only decoding is required to detect and correct errors, eliminating the need for real-time encoding and reducing the power and time requirements of scrub operations.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If traditional ECC encoding and decoding processes are used during scrub operations, then error correction capability is maintained, but operation time increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidoperation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent removes the encoding step from the scrub operation sequence, retaining only decoding and correction. This streamlining of the process reduces the number of computational cycles required, thereby decreasing operation time while maintaining error correction functionality.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

By performing encoding beforehand during normal write operations, the patent ensures that encoded data is already in the correct format when scrub operations occur. This preliminary preparation eliminates the need for time-consuming encoding during scrubs, reducing operation time while preserving reliability.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If sufficient storage space is allocated for ECC operations, then error correction capability is maintained, but storage capacity for user data decreases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidstorage capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent implements a partial ECC approach where only parity bits are corrected during scrub operations, rather than re-encoding the entire data block. This partial correction strategy maintains error correction capability for the most critical elements (parity bits) while minimizing the additional storage overhead and maximizing user data capacity.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11360848B2Error correction code scrub scheme
Publication Date: 2022.06.14 MICRON TECHNOLOGY INC
  • US11360848B2 patent drawing
  • US11360848B2 patent drawing
  • US11360848B2 patent drawing

AI summary

Methods, systems, and devices for an error correcting code scrub scheme are described. A memory device may correct an error associated with a first data bit or a first parity bit of a plurality of data bits and a plurality of parity bits, respectively. The memory device may correct the error by reading each of the plurality of data bits and the plurality of parity bits from a memory array, and determining that an error associated with a single bit exists. The memory device may then correct the determined single-bit error, and may write the corrected bit directly back to the memory array.