ECC Sector Configuration for 3D NAND Memory Yield
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Solution Overview
Problem
As semiconductor memory devices become more integrated, the number of defective memory cells increases, leading to decreased yield and performance, particularly due to inefficient error check and correction (ECC) schemes that do not account for varying operational characteristics of outer and inner memory cells in three-dimensional NAND flash memory devices.
Innovation Solution
The method involves rearranging data input-output order to uniformly distribute memory cells with worse characteristics within ECC sectors, thereby reducing the maximum error bit level and enhancing the repair rate of defective memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is increased through higher integration, then storage capability is improved, but the number of defective memory cells increases and yield decreases
Solution Approach 1:
The memory device divides memory cells into different groups (inner cells and outer cells) based on their spatial locations and characteristics. ECC sectors are configured to include a balanced mix of cells from different groups, segmenting the error correction process to handle different cell types appropriately. This segmentation allows the system to address defects in high-capacity integrated memory by treating different cell regions with tailored correction strategies.
2Device complexity
If conventional ECC schemes are used without considering cell characteristics, then implementation is simple, but error correction efficiency is poor due to varying operational characteristics of outer and inner cells
Solution Approach 1:
The patent applies different error correction strategies to different cell groups based on their local characteristics. Inner cells and outer cells are treated differently in terms of ECC sector configuration and error bit level distribution. The system configures ECC sectors to include substantially the same number of cells from each group, creating local quality variations in the error correction approach that match the local characteristics of different memory regions.
Solution Approach 2:
The system changes the parameter of ECC sector configuration to account for cell characteristics. By adjusting how cells are distributed among ECC sectors and considering the different error bit levels of inner versus outer cells, the system adapts the error correction parameters to match the actual operational characteristics of the memory device, thereby improving correction efficiency without requiring a complete redesign of the ECC scheme.
3Reliability
If data input-output order is rearranged to uniformly distribute error bit levels, then repair rate increases, but data access complexity increases
Solution Approach 1:
The system performs preliminary arrangement of data input-output order during the manufacturing or initialization phase, configuring ECC sectors to have uniform distribution of error bit levels before actual memory operations begin. This preliminary configuration ensures that when errors occur, the repair rate is maximized because the error distribution is already optimized. The complexity of data access is minimized because this arrangement is established once in advance rather than being dynamically recalculated during operations.
Data Source
AI summary
A memory cell array includes memory cells that are formed in vertical channels extended in a vertical direction with respect to a substrate. The vertical channels are arranged in a zigzag manner in parallel to the first direction. A read-write circuit is connected to the memory cells via bit lines. An address decoder decodes an address to provide decoded address signals to the read-write, circuit. The memory cells include outer cells and inner cells. A distance between one of the outer cells and a common source node is smaller than a distance between one of the inner cells and the common source node. Data of the memory cells are distributed among ECC sectors and a data input-output order of the memory cells is arranged such that each ECC sector has substantially the same number of the outer cells and the inner cells. Each ECC sector corresponds to an ECC operation unit.