Memory Controller ECC Select Circuit for Critical Bit Error Correction
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Solution Overview
Problem
Existing memory devices face reliability issues due to errors in stored data, which can reduce the overall reliability of the memory system.
Innovation Solution
A memory controller that encodes and decodes data using error correction code (ECC) mechanisms, specifically selecting between first and second ECC conversion data based on an ECC select signal to correct errors in critical bits within the data burst.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction code (ECC) is applied to all bits in data burst, then reliability is improved, but device complexity and processing time increase
Solution Approach 1:
The patent applies different ECC processing strategies to different parts of the data burst. Critical bits (such as most significant bits or specific bit positions) receive full ECC correction processing, while non-critical bits use simplified or no ECC processing. This localized differentiation improves overall reliability for important data while reducing the complexity and processing overhead compared to applying ECC uniformly to all bits.
2Reliability
If ECC processing is performed on all data bits, then error correction capability is improved, but operating speed decreases
Solution Approach 1:
The patent performs ECC processing selectively on critical bits rather than all bits in the data burst. By identifying and prioritizing error correction for only the most important bits (such as MSBs or bits at specific positions), the system maintains strong error correction capability for essential data while significantly reducing the processing time and operational overhead associated with full-bit ECC processing.
Solution Approach 2:
The patent applies partial ECC action by processing only a subset of bits (critical bits) rather than all bits. This partial processing approach provides sufficient error correction for the most important data elements while avoiding the excessive processing time that would result from applying ECC to every bit in the data burst, thus balancing reliability and speed.
3Productivity
If selective ECC processing is applied to critical bits only, then processing speed is improved, but reliability for non-critical bits deteriorates
Solution Approach 1:
The patent acknowledges that different bits have different importance levels and applies appropriate ECC processing accordingly. Critical bits receive full ECC protection to ensure high reliability, while non-critical bits use simplified processing. This differentiated approach accepts reduced protection for non-critical bits as a necessary trade-off to achieve the processing speed improvements and overall system efficiency.
Data Source
AI summary
A memory controller includes an error correction code (ECC) circuit configured to receive a data burst and generate first ECC data or second ECC data, and a processor configured to control operations of the ECC circuit. The ECC circuit includes an ECC select circuit configured to select and output one of first ECC conversion data and second ECC conversion data, based on an ECC select signal from outside the memory controller, and an ECC conversion circuit configured to generate the first ECC data by encoding the data burst, based on the first ECC conversion data, or generate the second ECC data by encoding the data burst, based on the second ECC conversion data. The second ECC conversion data is set to be capable of correcting an error generated in one or more preset protected bits among bits included in each of pieces of partial data included in the data burst.