ECC Error Detection Circuit Self-Test Using Bit-Flip Signatures
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Solution Overview
Problem
Complex processing systems, such as micro-controllers, face challenges in effectively monitoring and managing errors, particularly in safety-critical components like error correction code (ECC) circuits, which can malfunction and fail to detect or incorrectly signal errors.
Innovation Solution
A processing system with an error detection circuit that calculates and verifies ECC bits, generates syndromes, and uses bit-flip signatures to accurately identify and correct errors, supplemented by a test circuit that verifies the error detection circuit's functionality during a test mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction code (ECC) circuits are used in safety-critical components, then reliability is improved, but the complexity of monitoring and managing errors increases
Solution Approach 1:
The error detection circuit performs self-verification by calculating ECC bits and generating syndromes to monitor its own functionality. The circuit independently detects errors in its error detection process, enabling self-diagnosis without external intervention.
Solution Approach 2:
The circuit generates feedback signals including syndromes and bit-flip signatures that indicate the status of error detection. These feedback mechanisms allow the system to monitor and respond to errors in real-time, improving reliability while maintaining manageable complexity through structured information flow.
2Measurement precision
If bit-flip signatures are used to identify error positions, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The error detection process is segmented into distinct functional blocks: ECC bit calculation, syndrome generation, and bit-flip signature generation. Each block handles a specific aspect of error detection, improving precision while keeping individual components simple and manageable.
Solution Approach 2:
The circuit uses syndromes as an intermediate dimension to bridge raw error data and actionable error position information. By introducing syndrome bits as a separate layer of analysis, the system achieves precise error positioning without directly complicating the core detection logic.
3Reliability
If test circuits are added to verify error detection circuit functionality, then reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The test circuit is merged with the error detection circuit, allowing the same hardware structure to serve dual purposes: normal error detection during operation and self-verification during test modes. This integration improves reliability through verification while minimizing additional complexity.
Solution Approach 2:
The error detection circuit is designed with multi-functionality to operate in both normal detection mode and self-verification test mode. The circuit universally handles error detection tasks and its own verification, eliminating the need for completely separate test hardware and reducing overall system complexity.
Data Source
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AI summary
A processing system is described. The processing system comprises an error detection circuit (46) configured to receive data bits (DATA) and ECC bits. The error detection circuit (46) calculates further ECC bits as a function of the data bits (DATA) and generates a syndrome (SYN) by comparing the calculated ECC bits with the received ECC bits. When the syndrome (SYN) corresponds to one of N + K single bit-flip reference syndromes, the error detection circuit (46) asserts a first error signal (ERR1), and asserts one bit of a bit-flip signature (SIG) corresponding to a single bit-flip error indicated by the respective single bit-flip reference syndrome. The processing system further comprises a test circuit (48) configured to provide, during a test-mode (TM), a sequence of patterns (PAT) to the error detection circuit (46), each pattern (PAT) comprising data bits (DATA) and ECC bits. Specifically, the test circuit (48) obtains a first pattern (PAT) without ECC errors, provides the first pattern (PAT) to the error detection circuit (46) and verifies whether the first error signal (ERR1) is de-asserted and all bits of the bit-flip signature (SIG) are de-asserted. Moreover, the test circuit (48) obtains a sequence of N + K further bit-flip signatures (FSIG), each further bit-flip signature (SIG) having asserted a single bit. Moreover, the test circuit obtains (1008, 1014) for each further bit-flip signature (FSIG) a respective second pattern (PAT), wherein each second pattern (PAT) corresponds to a pattern having a single bit flipped with respect to a reference pattern at the positions of the single asserted bit of the respective further bit-flip signature (FSIG). The test circuit provides each second pattern (PAT) to the error detection circuit (46) and verifies whether the first error signal (ERR1) is asserted and the bit-flip signature (SIG) corresponds to the respective further bit-flip signature.