ECC Signal Line Layout for Simultaneous Switching Noise
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Solution Overview
Problem
Signal transmission/reception circuits face challenges in ensuring error correction capability for both simultaneous switching errors and multiple errors occurring on a particular signal line, particularly due to noise and performance degradation in LSIs.
Innovation Solution
A signal transmission/reception circuit design that includes a transmission circuit generating error checking and correcting codes and transmitting them over separate signal lines, ensuring that bits of the same code word are not output simultaneously, and a reception circuit performing error correction using stored ECC codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If all bits of the same code word are transmitted via the same signal line to reduce simultaneous switching errors, then simultaneous switching noise resistance is improved, but the probability of multiple errors on a particular signal line increases
Solution Approach 1:
The code word bits are segmented and distributed across multiple signal lines. Specifically, bits are arranged in a matrix format where rows correspond to signal lines and columns correspond to time slots, ensuring that not all bits of the same code word travel on the same physical line, thus balancing noise resistance and error correction capability
Solution Approach 2:
The transmission is transformed from a single-dimension (all bits on one line) to a two-dimensional arrangement (matrix of signal lines and time slots). This dimensional change allows bits to be distributed across multiple lines while maintaining temporal structure, resolving the contradiction between noise resistance and error correction
2Reliability
If error checking and correcting codes are added to each word to enable error correction, then error correction capability is improved, but the complexity of the transmission protocol increases
Solution Approach 1:
The error correction capability is merged with the existing data transmission structure by using the same signal lines for both data and ECC codes. The matrix arrangement combines data bits and ECC bits in a unified transmission framework, avoiding the need for separate dedicated error correction channels and reducing overall system complexity
Data Source
AI summary
A data buffer section stores input words, and outputs them to a first signal line group in order. An error checking and correcting code is generated that has the same number of bits as the words. Some bits are not to be output at the same time within the range of the first and second signal line groups or within the range of a partial signal line group included in the first and second signal line groups. A code transmission section outputs the error checking and correcting code to different signal lines of the second signal line group respectively, such that a plurality of bits in a code word are not output at the same time within the range of the first and second signal line groups or within the range of a partial signal line group included in the first and second signal line groups.