ECC Evaluation Circuit for Single-Cycle High-Frequency Memory
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Solution Overview
Problem
High-frequency memory devices face significant logic delay in calculating and comparing error correcting codes (ECCs), which necessitates either reducing clock frequency or adding additional clock cycles, both of which are undesirable as they impact bandwidth or efficiency.
Innovation Solution
Implementing a logic path that uses dynamic logic gates to complete ECC calculations and comparisons within a single clock cycle, eliminating the need for additional clock periods by enabling calculations as signals are received, rather than synchronizing with a clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If static logic gates are used for ECC calculation and comparison, then the circuit design is simple and reliable, but the logic delay increases requiring additional clock cycles
Solution Approach 1:
The patent applies dynamic logic gates instead of static logic gates for ECC calculation and comparison. The dynamic logic circuit evaluates ECC terms as signals are received and produces the final ECC valid signal within the same clock cycle, eliminating the need for additional clock cycles while maintaining circuit reliability through structured dynamic logic design.
Solution Approach 2:
The patent performs preliminary evaluation of ECC terms using dynamic logic gates that prepare intermediate results during the same clock cycle in which input signals are received. This preliminary action allows the complete ECC calculation and comparison to finish within one clock cycle, preventing time loss without compromising reliability.
2Measurement precision
If additional clock cycles are added for ECC validation, then calculation accuracy is maintained, but bandwidth and processing efficiency decrease
Solution Approach 1:
The patent implements continuous ECC validation by using dynamic logic gates that process ECC terms and complete the validation within the same clock cycle in which data is received. This continuous action eliminates idle clock cycles, maintaining both validation accuracy and maximum memory bandwidth utilization.
Solution Approach 2:
The patent rushes through the ECC calculation and comparison process by using dynamic logic that evaluates all ECC terms and produces the validation result within the same clock cycle, skipping the need for additional clock cycles and thereby maintaining high productivity without sacrificing accuracy.
3Speed
If clock frequency is reduced to accommodate ECC calculation delay, then logic delay is reduced, but operating speed and bandwidth decrease
Solution Approach 1:
The patent uses dynamic logic gates that can evaluate ECC terms and complete validation within the same clock cycle at high frequencies. This dynamic approach reduces the effective logic delay without requiring clock frequency reduction, thereby maintaining high operating speed and bandwidth.
Data Source
AI summary
Error correcting codes (ECCs) have been proposed to be used in high frequency memory devices to detect errors in signals transmitted between a memory controller and a memory device. For high frequency memory devices, ECCs have delay characteristics of greater than one clock cycle. When the delay exceeds one clock cycle but is much less than two clock cycles, an entire second clock cycle must be added. By calculating and comparing the ECC value in a static logic circuit and a dynamic logic circuit, the logic delay is substantially reduced. In addition, the ECC value may be calculated and compared using two sets of static logic gates, where the second static logic gate is clocked by a clock signal that is delayed relative to the clock signal of the first set of logic gates.