SRAM Buffer for ECC Multi-bit Data Storage in HDD Read Channels
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Solution Overview
Problem
Existing hard disk drive (HDD) systems face challenges in efficiently storing and processing multi-bit data, leading to increased circuit area and high demands on performance and cost due to the need for high-speed memory to handle the high transfer rate of AD converter data, which is not effectively addressed by prior art methods.
Innovation Solution
Implementing a buffer circuit to hold and parallelize multi-bit data from the AD converter before decoding, using a SRAM for error correction, and optimizing the memory bus width to reduce clock frequency and store multi-bit data without increasing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated memory is used to store AD converter output values, then the multi-bit data can be stored for error recovery processes, but the circuit area increases
Solution Approach 1:
The patent applies multi-functionality by enabling the SRAM buffer to serve dual purposes: storing multi-bit AD converter data for error recovery processes and performing error correction operations. This eliminates the need for separate dedicated memory blocks, thereby maintaining reliability while reducing circuit area.
Solution Approach 2:
The patent merges the storage function for multi-bit data with the error correction function by using the same SRAM buffer for both purposes. The buffer is configured to store AD converter output values and subsequently use these stored values for error recovery, combining what were previously separate functional blocks into a unified structure.
2Loss of information
If high-speed memory is used to store AD converted data at high transfer rate, then the data can be stored without losing information, but the cost and performance demands increase
Solution Approach 1:
The patent applies preliminary action by storing the multi-bit AD converter data in the SRAM buffer before the data is fully processed or decoded. This preliminary storage ensures that the data is captured and preserved at the high transfer rate without requiring subsequent high-speed memory operations, thereby maintaining data integrity while reducing overall system complexity.
Solution Approach 2:
The SRAM buffer acts as an intermediary between the high-speed AD converter and the subsequent processing stages. It receives the high-rate multi-bit data and holds it temporarily, serving as a buffer that decouples the high-speed data generation from the slower processing requirements, thus maintaining data integrity without imposing high performance demands on the entire system.
Data Source
AI summary
An embodiment in accordance with the present invention enables storing in a memory, multi-bit data corresponding to analog signals read from a medium before being converted to single-bit data as recorded data. In an embodiment of the present invention, an AD converter is configured to convert analog signals from a magnetic disk to multi-bit data. A buffer circuit holds successively multi-bit data transferred from the AD converter toward a Viterbi decoder, and outputs the held plural multi-bit data in parallel. A SRAM for ECC is used for storing multi-bit data transferred from the buffer circuit.