ECC Circuit Fast Decoding Status Flag for Memory Error Correction
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently correcting errors in data stored within them, particularly when the error exceeds the error correction capability of the existing error correction code (ECC) circuits, leading to uncorrectable errors and increased latency in generating decoding status flags.
Innovation Solution
The implementation of a memory device with an ECC circuit that includes a syndrome generator, a syndrome decoding circuit, a correction logic circuit, and a fast decoding status flag (DSF) generator, which uses a simplified-parity-check matrix to parallelize the generation of error-corrected data and decoding status flags, reducing latency by eliminating the need for an error vector in generating the DSF.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the ECC circuit uses a traditional syndrome decoding approach that generates the decoding status flag based on the error vector, then the decoding status is accurately determined, but the latency in generating the decoding status flag increases
Solution Approach 1:
The patent segments the parity-check matrix into multiple sub-matrices, where each sub-matrix corresponds to a specific error pattern type. This segmentation allows the syndrome decoding circuit to quickly identify which sub-matrix contains the matching syndrome pattern, thereby determining the decoding status without waiting for complete error vector generation. The segmentation enables parallel processing of different error pattern possibilities, reducing the time to generate the decoding status flag while maintaining accurate determination through systematic classification of error types.
2Reliability
If the ECC circuit processes errors that exceed its correction capability, then comprehensive error detection is achieved, but the number of uncorrectable errors increases and performance degrades
Solution Approach 1:
The patent implements partial error correction by focusing on detecting and correcting specific error patterns that are within the ECC circuit's capability, rather than attempting to handle all possible error types uniformly. The syndrome decoding circuit is designed to efficiently identify and correct common error patterns while quickly identifying uncorrectable errors. This selective approach allows the system to maintain high performance for correctable errors while still providing comprehensive error detection, thereby improving overall productivity even when some errors exceed correction capability.
Data Source
AI summary
Disclosed is a memory device which includes a memory cell array that stores first data and first parity data, an error correction code (ECC) circuit that performs ECC decoding based on the first data and the first parity data and outputs error-corrected data and a decoding status flag, and an input/output circuit that provides the error-corrected data and the decoding status flag to a memory controller. The ECC circuit includes a syndrome generator that generates a syndrome based on the first data and the first parity data, a syndrome decoding circuit that decodes the syndrome to generate an error vector, a correction logic circuit that generates the error-corrected data based on the error vector and the first data, and a fast decoding status flag (DSF) generator that generates the decoding status flag based on the syndrome, without the error vector.