ECC Engine Sub-Codeword Grouping for DRAM Bit Error Correction
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Solution Overview
Problem
The increasing bit errors in DRAM devices due to reduced fabrication design rules lead to decreased yield and performance issues in semiconductor memory devices, necessitating an effective error correction mechanism.
Innovation Solution
An error correction circuit utilizing an error correction code (ECC) represented by a generation matrix, which generates first parity data to correct error bits in main data by dividing data bits into sub codeword groups and using column vectors to restrict the location of miscorrected bits, thereby improving error correction efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fabrication design rules are reduced to increase memory density, then storage capacity is improved, but bit error rate increases
Solution Approach 1:
The main data is divided into multiple sub-codeword groups, and the ECC column vectors are segmented into multiple code groups. Each code group corresponds to specific sub-codeword groups, enabling localized error correction and preventing error propagation across the entire data set.
Solution Approach 2:
Different code groups in the ECC have different structures optimized for specific purposes: some code groups are designed to detect errors in particular sub-codeword groups, while others are designed to prevent miscorrection. This local differentiation allows the system to handle errors in specific regions without affecting overall data integrity.
2Reliability
If conventional ECC is used for error correction, then error detection capability is provided, but miscorrected bits may occur reducing correction accuracy
Solution Approach 1:
The ECC column vectors are pre-configured with specific structures that anticipate potential error patterns. By designing code groups with predetermined properties before data storage, the system can immediately identify and correct errors without risking miscorrection, as the correction logic is already optimized for the expected error types.
Solution Approach 2:
The ECC engine uses the structured column vectors to generate feedback information about error locations and types. This feedback mechanism allows the system to verify corrections and prevent miscorrection by cross-checking error patterns against the predefined code group structures.
3Measurement precision
If data is divided into sub codeword groups with structured ECC, then error correction precision is improved, but device complexity increases
Solution Approach 1:
The divided code groups serve multiple functions: they can detect errors in specific sub-codeword groups, prevent miscorrection in other groups, and work collectively to correct errors across the entire data set. This multi-functionality reduces the need for separate error handling mechanisms for different error scenarios.
Solution Approach 2:
Instead of designing a single complex ECC structure that handles all possible error scenarios, the system uses multiple simpler code groups that each handle specific error types or locations. This partial action approach divides the complexity into manageable segments while achieving comprehensive error protection.
Data Source
AI summary
An error correction circuit of a semiconductor memory device including a memory cell array includes an error correction code (ECC) memory that stores an ECC and an ECC engine. The ECC is represented by a generation matrix. The ECC engine generates first parity data based on main data using the ECC, and corrects at least one error bit in the main data read from the memory cell array using the first parity data. The main data includes a plurality of data bits divided into a plurality of sub codeword groups. The ECC includes a plurality of column vectors divided into a plurality of code groups corresponding to the sub codeword groups. The column vectors have elements configured to restrict a location of a sub codeword group in which a mis-corrected bit occurs, in which the mis-corrected bit is generated due to error bits in the main data.