ECC Symbol Reliability Decoding for PAM4 Burst Error Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing error correction codes in high-speed data transmission, such as PCIe 6.0, are limited in correcting burst errors and cannot correct two errors occurring within one symbol, leading to increased error rates and performance degradation.
Innovation Solution
An electronic device and method that generate bit and symbol reliability values based on voltage levels of analog signals to enhance error correction performance by efficiently identifying and correcting errors in error correction code symbols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC is used in PCIe 6.0 with PAM4 signaling, then data transmission can be performed, but error correction capability is insufficient for burst errors and multiple errors within one symbol
Solution Approach 1:
The invention segments the error correction process by dividing ECC symbols into multiple groups and applying different correction strategies to each group. This allows the system to handle burst errors and multiple errors within one symbol by treating different segments differently, thereby improving overall error correction capability without requiring a complete redesign of the ECC structure.
Solution Approach 2:
The invention performs preliminary error detection and identification before correction by first detecting errors in ECC symbols, then identifying which symbols contain multiple errors or burst errors. This preliminary action allows the system to prepare appropriate correction strategies in advance, improving reliability without adding significant complexity to the overall ECC structure.
2Reliability
If error correction is performed on all ECC symbols, then error correction completeness is improved, but error correction time increases
Solution Approach 1:
The invention applies local quality by differentiating error correction approaches based on the specific characteristics of each ECC symbol group. Instead of applying uniform correction to all symbols, the system identifies groups with different error patterns (e.g., burst errors vs. single errors) and applies appropriate correction methods to each, improving completeness while reducing overall correction time.
Solution Approach 2:
The invention performs partial error correction by first correcting errors in identified error-prone symbol groups, then performing additional correction on remaining symbols if needed. This partial action approach ensures critical errors are corrected promptly while maintaining the option for complete correction, thereby balancing completeness with time efficiency.
3Speed
If transmission speed is increased using PAM4 signaling, then data rate is improved, but error occurrence rate increases
Solution Approach 1:
The invention implements feedback mechanisms by continuously monitoring error patterns in received PAM4 signals and adjusting error correction strategies accordingly. The system uses feedback from error detection results to identify symbols requiring additional correction attention, thereby maintaining high transmission speeds while compensating for increased error occurrence through adaptive correction.
Solution Approach 2:
The invention changes parameters of the error correction process dynamically based on observed error patterns. By adjusting correction thresholds, grouping strategies, and correction intensity based on real-time error statistics from PAM4 transmission, the system maintains high data rates while effectively correcting the increased error occurrence inherent in faster signaling.
Data Source
AI summary
An electronic device may include a reception circuit configured to generate a plurality of reception data bits based on a voltage level of an analog signal received through a link, and to generate a plurality of bit reliability values indicating probabilities of error occurrence of the plurality of reception data bits based on the voltage level of the analog signal, an alignment circuit configured to group the plurality of reception data bits into a plurality of error correction code (ECC) symbols, and to generate a plurality of symbol reliability values indicating probabilities of error occurrence of the plurality of ECC symbols based on the plurality of bit reliability values, and a decoding circuit configured to correct errors of the plurality of ECC symbols based on the plurality of symbol reliability values.