ECC Circuit Using Estimation Syndromes for Chip Error Localization
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Solution Overview
Problem
Existing semiconductor memory devices, particularly DRAMs, face challenges in efficiently correcting and managing errors that occur in memory modules, especially when the number of parity data sets is insufficient to identify the specific memory chip generating errors.
Innovation Solution
An error correction circuit is implemented using a parity generation matrix and parity check matrix to generate syndromes, estimation syndromes, and comparison methods to accurately identify and correct errors in memory chips, even when parity data is limited.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the number of parity data sets is reduced to lower cost and simplify the system, then the device complexity and cost decrease, but the ability to identify the specific memory chip generating errors deteriorates
Solution Approach 1:
The patent segments the error identification process into two distinct stages: first generating a syndrome to detect the presence of errors, then generating an estimation syndrome to identify the specific memory chip location. This segmentation allows the system to use fewer parity data sets while maintaining accurate error identification capability by separating the detection function from the localization function.
Solution Approach 2:
The patent introduces an intermediary estimation syndrome generation process that acts as a bridge between the limited parity data and the full error identification requirement. The estimation syndrome serves as an intermediate computational step that enables accurate chip identification without requiring a proportional increase in parity data sets, thus resolving the contradiction between reduced complexity and maintained precision.
2Measurement precision
If more parity data sets are added to improve error identification accuracy, then the measurement precision of error location improves, but the device complexity and resource requirements increase
Solution Approach 1:
The patent performs preliminary error detection through syndrome generation before proceeding to error location identification. This preliminary action allows the system to filter out error-free data paths early, enabling subsequent estimation syndrome generation to focus only on potential error sources, thereby achieving accurate error location without requiring all parity data sets to be actively processed simultaneously.
Solution Approach 2:
The patent implements partial action by using a reduced set of parity data sets for syndrome generation, then compensating through the estimation syndrome process that mathematically derives additional identification information. This approach achieves full error location accuracy through partial data processing combined with computational estimation, avoiding the need to implement excessive parity data sets.
3Device complexity
If the error correction circuit uses fewer parity bits to reduce complexity, then the device complexity decreases, but the reliability of error correction deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where the estimation syndrome is generated based on the initial syndrome and then fed back into the correction process. This feedback loop allows the system to iteratively refine error identification accuracy, enabling reliable error correction with fewer parity bits by continuously improving the estimation based on previous computational results.
Solution Approach 2:
The patent changes the computational parameters of the error correction process by introducing the estimation syndrome as an additional computational parameter. This parameter change transforms the error correction approach from direct parity-based correction to an estimation-based method, maintaining reliability with reduced parity bit requirements through mathematical transformation of the correction parameters.
Data Source
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AI summary
An error correction circuit, including an error correction code (ECC) encoder configured to generate parity data corresponding to main data based on a parity generation matrix, and to output a codeword including the main data and the parity data to a plurality of memory devices; and an ECC decoder configured to: read the codeword from the plurality of memory devices, generate a syndrome corresponding to the codeword based on a parity check matrix, detect an error pattern based on the syndrome, generate a plurality of estimation syndromes corresponding to the error pattern using a plurality of partial submatrices included in the parity check matrix, and correct an error included in the read codeword based on a result of a comparison between the syndrome and the plurality of estimation syndromes.