ECC Syndrome Comparison for Uncorrectable Memory Error Detection
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Solution Overview
Problem
Existing memory systems fail to detect uncorrectable errors, leading to compromised data being transmitted to host systems without alerts, which can compromise safety-related applications.
Innovation Solution
Implementing an ECC circuit with a syndrome check circuit, bit modification and detection circuit, and uncorrectable error detection circuit to compare syndrome bits generated at different times, generating flags to identify and alert host systems to uncorrectable errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC schemes are used for error correction, then single-bit errors can be corrected, but uncorrectable errors (multiple bit errors) cannot be detected due to aliasing
Solution Approach 1:
The patent segments the ECC verification process into multiple independent components: syndrome bit generation, syndrome bit comparison, and uncorrectable error detection. By dividing the verification into separate stages (first syndrome bits from stored data, second syndrome bits from retrieved data, and their comparison), the system can detect uncorrectable errors without requiring a completely new ECC structure.
Solution Approach 2:
The patent performs preliminary action by generating and storing first syndrome bits when data is written to memory, before any potential errors occur. These pre-stored syndrome bits serve as a reference for later comparison with second syndrome bits generated during read operations, enabling detection of uncorrectable errors that would otherwise go undetected.
2Reliability
If no uncorrectable error detection is implemented, then the system remains simple, but compromised data is transmitted to host systems without alerts
Solution Approach 1:
The patent introduces an intermediary mechanism - the syndrome bit comparison circuit - that acts as a mediator between the traditional ECC correction process and the host system. This intermediary compares pre-stored syndrome bits with newly generated syndrome bits and generates an uncorrectable error indicator, providing an additional layer of protection without fundamentally changing the existing ECC infrastructure.
Solution Approach 2:
The patent implements partial action by adding only the necessary uncorrectable error detection functionality rather than completely replacing the existing ECC system. The solution adds syndrome bit comparison and uncorrectable error indication capabilities while maintaining compatibility with existing single-bit error correction mechanisms, achieving enhanced protection with minimal additional complexity.
Data Source
AI summary
Methods, systems, and devices for uncorrectable error detection in memory systems are described. A memory system may perform a syndrome check to compare a first syndrome with a second syndrome, the first syndrome being generated as part of a first error control operation performed on data and the second syndrome being generated as part of a second error control operation performed on the data. Based on performing the syndrome check, the memory system may generate a first flag that indicates whether the first syndrome is equivalent to the second syndrome. The memory system may generate a second flag that indicates whether the second error control operation resulted in one or more bits of the data being modified. Based on the first and second flags, the memory system may generate a third flag that indicates whether an uncorrectable error is detected in the data during the second error control operation.