ECC Decoding Threshold Adaptation for Fast-Fail NAND Reads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing error correction mechanisms in non-volatile memory devices, such as NAND flash SSDs, face challenges in maintaining data integrity and reliability while adhering to stringent latency requirements, especially in fast fail modes where variable maximum latency is a concern, leading to increased codeword failure rates.
Innovation Solution
The implementation of a method that dynamically adjusts bit flipping thresholds based on the remaining number of iterations and latency requirements during decoding operations in fast fail mode, allowing for adaptive error correction to ensure successful decoding within the given latency constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a fixed maximum number of iterations is used for ECC decoding, then the decoding process is simple to implement, but the codeword failure rate increases when latency requirements vary
Solution Approach 1:
The patent implements dynamic iteration adaptation by allowing the ECC decoder to adjust the number of iterations based on remaining latency budget. The decoder transitions from a static fixed iteration count to a dynamic configuration where the maximum number of iterations is recalculated based on actual latency requirements and decoding progress, thereby reducing codeword failures while maintaining implementation feasibility.
Solution Approach 2:
The patent changes the parameter of iteration count from a fixed value to a dynamically adjustable parameter. By modifying the maximum number of iterations parameter based on remaining latency budget and decoding performance, the system adapts to varying latency requirements and reduces codeword failure rates without requiring complete redesign of the decoding architecture.
2Reliability
If the number of iterations is increased to reduce codeword failures, then reliability improves, but latency requirements may not be met
Solution Approach 1:
The patent implements feedback mechanisms where the decoder monitors decoding progress and remaining latency budget at each iteration. Based on this feedback, the system dynamically adjusts the number of remaining iterations to perform, ensuring that decoding continues long enough to achieve reliable error correction while stopping before exceeding latency requirements. This feedback-driven adaptation resolves the contradiction between reliability and latency.
Solution Approach 2:
The system transitions from static iteration counting to dynamic iteration management where the maximum number of iterations is continuously adjusted based on real-time decoding performance and latency constraints. This dynamic approach allows the decoder to use more iterations when needed for reliability while automatically reducing iterations when latency budget is exhausted, preventing both codeword failures and latency violations.
3Reliability
If dynamic adjustment of bit flipping thresholds is implemented, then error correction performance is optimized, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing threshold values for different decoding scenarios before actual decoding begins. When dynamic adjustment is needed, the system selects from pre-computed threshold sets based on current iteration count and latency budget, avoiding the need for complex real-time threshold calculations during decoding. This reduces implementation complexity while maintaining optimized error correction performance.
Data Source
AI summary
Disclosed are devices, systems and methods for improving fast fail support for error correction in non-volatile memory. An exemplary method includes (a) receiving a codeword from a read operation in a fast fail mode, (b) initially configuring a maximum number of iterations (Nmax) and a set of values for a plurality of bit flipping thresholds for performing a decoding operation on the codeword, (c) performing a plurality of decoding iterations (N), each iteration using a subset of bit flipping thresholds, (d) calculating a remaining number of iterations (Nrem) as a difference between Nmax and N, (e) reconfiguring, based on Nrem and a latency requirement of the read operation in the fast fail mode, the set of values for the plurality of bit flipping thresholds to restart the decoding operation, and (f) repeating operations (c) through (e) until the codeword is successfully decoded or Nrem is less than or equal to 0.