Combined ECC and TMBIST for Memory Fault Detection
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Solution Overview
Problem
Current memory fault detection methods, such as ECC and memory scrubbing with bit spreading, are insufficient for high-safety applications due to high error rates and uncorrectable multi-bit faults, especially in small technology nodes where bias temperature instability (BTI) affects inactive memory regions, leading to potential system failures.
Innovation Solution
Combining transparent memory built-in self-test (TMBIST) with error correction codes (ECC) and memory scrubbing, where each read access is followed by an XOR operation, using status bits to store information about XOR'ed bits, allowing for concurrent fault detection and correction during active application modes without disturbing the application, and distributing TMBIST marches over the allotted run time to mitigate BTI effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC and memory scrubbing are used to detect and correct faults, then reliability is improved, but inactive memory regions accumulate faults due to BTI effects
Solution Approach 1:
The patent implements periodic memory scrubbing operations that actively write test patterns to and read from memory cells at scheduled intervals. This periodic activation prevents BTI accumulation by regularly flipping bits in inactive regions, while ECC codes correct any errors detected during these scrubbing operations, thus resolving the contradiction between maintaining reliability and preventing BTI-induced faults.
2Reliability
If memory scrubbing is performed frequently to prevent fault accumulation, then reliability is improved, but power consumption and performance overhead increase
Solution Approach 1:
The patent applies partial scrubbing by selectively targeting only certain memory regions or using simplified test patterns rather than comprehensive testing of all memory cells. This reduces the frequency and intensity of scrubbing operations to minimal levels needed to prevent fault accumulation, thereby lowering power consumption while maintaining adequate reliability.
Solution Approach 2:
The system dynamically adjusts scrubbing parameters such as scrubbing frequency, test pattern complexity, and targeted memory regions based on operational conditions, error rates, and power availability. This allows the system to optimize the balance between reliability maintenance and power consumption by changing operational parameters rather than using fixed aggressive scrubbing.
3Reliability
If transparent memory BIST is implemented to detect faults during active operation, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent designs the memory controller to perform dual functions: normal memory access control and BIST operations. The same control logic, address generation, and data path infrastructure are reused for both application-mode memory access and self-test operations. This multi-functionality enables concurrent fault detection during active operation without requiring separate dedicated BIST hardware, thus improving reliability while minimizing the increase in device complexity.
Data Source
AI summary
Embodiments combine error correction code (ECC) and transparent memory built-in self-test (TMBIST) for memory fault detection and correction. An ECC encoder receives input data and provides ECC data for data words stored in memory. Input XOR circuits receive the input data and output XOR'ed data as payload data for the data words. Output XOR circuits receive the payload data and output XOR'ed data. An ECC decoder receives the ECC data and the XOR'ed output data and generates error messages. Either test data from a controller running a TMBIST process or application data from a processor executing an application is selected as the input data. Either test address/control signals from the controller or application address/control signals from the processor are selected for memory access. During active operation of the application, memory access is provided to the processor and the controller, and the memory is tested during the active operation.