ECC Word Layout for Dual-Level Memory Error Correction
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Solution Overview
Problem
Memory devices, particularly magnetic random access memories (MRAMs), experience higher inherent random errors during access operations compared to dynamic random access memories (DRAMs), leading to inefficiencies in error correction and a need for system-level error correction to ensure error-free operation.
Innovation Solution
The implementation of a memory device with dual levels of error correction: a first level of device-level error correction within the memory device and a second level of system-level error correction, where the first level is orthogonal to the second, allowing for efficient correction of errors by distributing data output across multiple input/output pads and utilizing ECC words to improve error handling and processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If device-level error correction is implemented in memory devices, then error correction capability is improved, but system-level error correction becomes necessary due to residual errors
Solution Approach 1:
The error correction system is segmented into two independent levels: device-level ECC correction circuitry within the memory device and system-level ECC correction circuitry in the external device. Each level handles a portion of the error correction task, with device-level correcting errors within individual ECC words and system-level correcting residual errors across multiple ECC words, thereby distributing the complexity across separate modules.
Solution Approach 2:
The patent introduces a second dimension of error correction by adding system-level ECC correction alongside device-level correction. Instead of relying on a single correction mechanism, the system operates in two dimensions: internal device-level correction and external system-level correction, creating a layered approach that handles errors at different granularities.
2Productivity
If multiple I/O pads are used for data output, then processing speed is improved, but errors may be injected at multiple pads impeding system-level correction
Solution Approach 1:
The device-level ECC correction circuitry performs partial error correction by correcting a first number of bit errors within each ECC word before output. This partial correction at the device level reduces the error burden on system-level correction, allowing multiple I/O pads to operate in parallel for speed while maintaining overall reliability through the combined correction capability.
3Reliability
If device-level ECC correction corrects errors within ECC words, then error-free operation is improved, but residual errors may still be passed to system-level correction
Solution Approach 1:
Device-level ECC correction performs preliminary error correction on each ECC word before data is output to I/O pads. This preliminary action corrects the most significant errors within individual ECC words, reducing the error rate before data leaves the memory device and minimizing the burden on system-level correction circuitry.
Solution Approach 2:
The device-level ECC correction circuitry acts as an intermediary between the memory array and the external system. It processes data internally, correcting errors before output, and serves as a bridge that prepares data for system-level correction by removing the most critical errors while allowing residual errors to pass through for secondary correction.
Data Source
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AI summary
In some examples, a memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction may be performed by the memory device on each of the ECC words associated with a page and a second level of error correction may be perform. ed on the data output by each of the input/output pads during a particular period of time. Each of the one or more input/output pads of the memory device may be configured to provide only one bit of data per ECC word to an external source during an access from an external source.