DRAM Controller ECC Write Latency via Transaction Arbiter
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Solution Overview
Problem
Conventional memory controllers experience latency issues with ECC write transactions, particularly at the end of a write turn when insufficient write transactions are available to interleave with ECC write transactions, leading to prolonged write turns and underutilization of the command/data bus, which degrades overall system performance.
Innovation Solution
A transaction arbiter schedules memory transactions across the command/data bus, determining when sufficient write transactions are available to mask ECC write transaction latencies. If insufficient, the arbiter caches ECC write transactions, allowing a subsequent read turn to begin and prioritizes them during the next write turn for interleaving with other write transactions, thereby reducing latency and bus bubbles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ECC write transactions are scheduled for execution at the end of a write turn, then all write transactions can be completed, but the command/data bus becomes underutilized and latency cannot be masked
Solution Approach 1:
The transaction arbiter defers ECC write transactions to subsequent write turns when insufficient write transactions are available for interleaving, performing the scheduling decision in advance to prevent bus underutilization and latency issues
Solution Approach 2:
The scheduling policy dynamically adjusts based on the number of available write transactions, transitioning from immediate scheduling to deferred scheduling when conditions change, thereby optimizing bus utilization
2Reliability
If the write turn is prolonged to complete remaining ECC write transactions, then all transactions can be processed, but the subsequent read turn is delayed reducing memory access speed
Solution Approach 1:
The arbiter performs preliminary scheduling decisions by deferring ECC write transactions to subsequent turns when write transaction availability is insufficient, preventing unnecessary prolongation of the current write turn and enabling timely read turns
3Loss of time
If ECC write transactions are interleaved with other write transactions, then latency can be masked, but insufficient write transactions are available at the end of the write turn
Solution Approach 1:
The transaction arbiter evaluates write transaction availability in advance and defers ECC write transactions to subsequent turns when insufficient transactions are available for effective interleaving, preventing wasted interleaving opportunities
Solution Approach 2:
The transaction arbiter acts as an intermediary that manages the scheduling conflict between ECC write transactions and other write transactions, making informed decisions about when to interleave and when to defer based on available transaction quantities
Data Source
AI summary
Techniques are disclosed for reducing the time required to read and write data to memory. Data reads and/or writes can be delayed when error correction code (ECC) bits, which are used to detect and/or correct data corruption, are written to memory. Writing ECC bits can take longer in some instances than writing data bits because an ECC write may involve a read/modify/write operation, as opposed to just simply writing the bits to memory. Some latencies associated with writing ECC bits can be hidden by interleaving ECC writes with data writes. However, if insufficient data writes are available for interleaving, hiding such latencies become difficult. Thus, various techniques are disclosed, for example, where ECC writes are deferred until a sufficient number of data writes become available for interleaving. By interleaving ECC writes, the disclosed techniques decrease the overall time required to read and write data to memory.