ECC Memory Write-Mask Pipelining to Cut Column Delay
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Solution Overview
Problem
As semiconductor memory feature sizes and voltage levels decrease, the margin of error for detecting data states in memory cells also decreases, leading to increased susceptibility to soft errors and other errors due to weak cells, such as variable refresh times.
Innovation Solution
The implementation of a memory apparatus and method that includes a memory array, a write driver, a data sense amplifier, an error control code circuit, and a control circuit. This configuration allows for the detection of two consecutive write mask operations and the pipelining of their execution, enabling the second write mask operation to begin before the first completes, thereby reducing the column-to-column delay and improving memory performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction code (ECC) is used with the memory, then data integrity is improved, but the time required for memory operations increases
Solution Approach 1:
The patent applies preliminary action by pre-charging the local input-output line during the ECC comparison period of the first read operation. This preparation is done in advance so that when the second read operation needs to access the memory, the I/O line is already ready, eliminating the need to wait for the first operation to fully complete. This resolves the contradiction by maintaining data integrity through full ECC processing while reducing the time impact through overlapping operations.
Solution Approach 2:
The patent implements continuity of useful action by allowing the second read operation to execute during the ECC comparison and correction phase of the first read operation. Instead of waiting for the first operation to complete, the system continuously processes the second operation, ensuring that memory bandwidth is utilized efficiently. This maintains data integrity through proper ECC handling while minimizing idle time and improving overall memory performance.
2Quantity of substance
If feature sizes of semiconductor memory are reduced, then memory capacity and area efficiency are improved, but the margin of error for detecting data states decreases
Solution Approach 1:
The patent applies beforehand cushioning by implementing error correction code (ECC) mechanisms that detect and correct errors before they propagate. The ECC circuit provides a safety margin that compensates for the reduced detection margin caused by smaller feature sizes. This allows the memory to maintain high capacity with small features while protecting against the increased susceptibility to soft errors through preemptive error detection and correction.
3Reliability
If consecutive write mask operations are executed sequentially, then data accuracy is maintained, but total execution time increases
Solution Approach 1:
The patent applies preliminary action by pre-charging the local input-output line during the ECC comparison phase of the first read operation. This preparation is performed in advance so that when the second operation needs to access the memory, the I/O infrastructure is already ready. This allows consecutive write mask operations to overlap in execution while maintaining data accuracy through proper ECC processing, thereby improving throughput without sacrificing reliability.
Solution Approach 2:
The patent implements continuity of useful action by allowing the second read operation to execute during the ECC comparison and correction phase of the first read operation. This continuous processing eliminates idle time between operations while maintaining data accuracy through proper error correction handling. The result is improved productivity through higher operation throughput while preserving data integrity.
Data Source
AI summary
Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.