ECC Write Masking Circuit for Multi-Bus-Width Memory Writes
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Solution Overview
Problem
Semiconductor memory devices face increased complexity and power consumption when configured to operate in multiple modes, particularly due to differences in write operations across varying data bus widths, which complicates error detection and correction processes.
Innovation Solution
The semiconductor device configures internal read/write circuitry to generate error detection codes based on a fixed number of bits independent of the I/O bus configuration, performs read operations to combine data subsets for write operations, and masks write operations for unchanged data to reduce current consumption by disabling column select signals and selectively driving data signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the semiconductor memory device is designed to operate in multiple modes with different data bus widths, then adaptability is improved, but device complexity increases
Solution Approach 1:
The error detection circuit is designed to generate error detection codes for a fixed number of bits regardless of the I/O bus configuration mode. This universal approach allows the same circuit to handle different bus widths (x4, x8, etc.) without requiring mode-specific complexity, thereby improving adaptability while controlling device complexity
2Adaptability or versatility
If the semiconductor memory device is designed to operate in multiple modes with different data bus widths, then adaptability is improved, but power consumption increases
Solution Approach 1:
The device performs read operations and generates error detection codes for a fixed number of bits even when the actual write data width is smaller. This partial action approach ensures that error detection is performed on all possible bits, and then masking is applied to prevent writing unnecessary data, thereby managing power consumption across different bus width configurations
3Device complexity
If error detection codes are generated based on fixed number of bits independent of I/O bus configuration, then device complexity is reduced, but loss of information may occur if not properly masked
Solution Approach 1:
A masking mechanism is introduced as an intermediary between the error detection circuit and the write operation. The masking logic uses the error detection codes to determine which data bits should be written, preventing both data loss and unnecessary writes. This intermediary layer maintains data integrity while allowing the error detection circuit to operate with fixed complexity
4Reliability
If read operations are performed to combine data subsets for write operations, then data reliability is improved, but productivity decreases
Solution Approach 1:
Read operations are performed in advance to retrieve data subsets that will be combined for the write operation. This preliminary action ensures that all necessary data is available and error detection is performed before the actual write, improving reliability. The timing and coordination of these operations are optimized to minimize the impact on overall productivity
Data Source
AI summary
An exemplary semiconductor device includes an input/output (I/O) circuit configured to combine data corresponding to a write command received via data terminals with a first subset of corrected read data retrieved from a memory cell array to provide write data. The exemplary semiconductor device further includes a write driver circuit configured to mask a write operation of a first bit of the write data that corresponds to a bit of the first subset of the read data and to perform a write operation for a second bit of the write data that corresponds to the data received via the data terminals.