Eccentric Via Stacking Layout for Low-Stress Bonding Pads
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Solution Overview
Problem
The increasing density of I/O pads on semiconductor dies complicates packaging, leading to stress issues due to high Coefficient of Thermal Expansion (CTE) values in conventional bonding structures, resulting in delamination and trace breaking.
Innovation Solution
The implementation of eccentric bonding structures, where a conductive bump and pad are formed with the pad being larger than the bump and having offset vias, reducing stress by misaligning the centerlines of the bump and pad, and further offsetting vias to distribute stress effectively through redistribution lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bonding structures with aligned vias are used, then manufacturing process is simple, but stress concentration occurs leading to delamination and trace breaking
Solution Approach 1:
The patent applies asymmetry by intentionally misaligning the via center from the conductive bump center in the bonding structure. This asymmetric via placement creates an offset configuration that distributes stress more effectively, preventing stress concentration at the via-bump interface and reducing delamination and trace breaking risks.
Solution Approach 2:
The patent introduces a lateral offset dimension to the via placement, moving from traditional vertical alignment to a two-dimensional offset configuration. This dimensional change allows stress distribution across a broader area, transforming the stress management approach from point-based to area-based distribution.
2Adaptability or versatility
If I/O pad density is increased to integrate more functions, then device functionality improves, but packaging difficulty increases
Solution Approach 1:
The patent segments the bonding structure into distinct functional zones: a larger conductive pad area for stress distribution, an offset via region for stress relief, and a conductive bump for electrical connection. This segmentation allows each component to optimize its function independently, accommodating high I/O pad density while maintaining packaging reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces stress in the bonding structure without increasing manufacturing costs or chip area, enhancing packaging yield and reliability.
Implementation Method 1
stress issues due to high Coefficient of Thermal Expansion (CTE) values in conventional bonding structures
Data Source
AI summary
A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.