Emitter-Coupled Logic Topology Using fT-Doublers for 50 GHz Operation
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Solution Overview
Problem
Conventional high-speed logic cells are unable to support high enough operating frequencies and consume excessive DC power, limiting their integration capabilities with advanced transistor processes like SiGe BiCMOS.
Innovation Solution
The use of fT-doubler circuits and cascode amplifier circuits, where multiple transistors are configured to behave as a single enhanced transistor, increasing the effective unity current gain frequency and enabling operation at higher frequencies while reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional high-speed logic cells are used, then logic function is achieved, but operating frequency is insufficient and DC power consumption is excessive
Solution Approach 1:
The logic cell is divided into multiple functional blocks including input circuitry, AND/OR gate circuitry, and output circuitry. Each block uses emitter-coupled transistor pairs with dedicated current sources, allowing independent optimization of each segment for high-frequency operation while managing power consumption locally throughout the circuit.
Solution Approach 2:
The patent employs transistor sizing ratios (such as W1/W2, W3/W4, W5/W6) to optimize current distribution and switching speeds. By adjusting width ratios and current source strengths, the circuit achieves higher operating frequencies while controlling power consumption through parameter optimization rather than increasing overall power supply.
2Adaptability or versatility
If conventional logic cells are used, then basic logic functions are performed, but integration capability with advanced transistor processes is limited
Solution Approach 1:
The logic cell design uses universal emitter-coupled transistor pairs that can implement multiple logic functions (AND, OR, NAND, NOR) by configuring the same basic circuit topology. This universal approach enables seamless integration with SiGe BiCMOS and other advanced processes while maintaining consistent performance across different logic functions through standardized current sources and transistor sizing.
3Productivity
If higher operating frequencies are achieved, then system performance is enhanced, but DC power consumption increases
Solution Approach 1:
The emitter-coupled logic circuit operates with periodic switching cycles where transistors alternately conduct and cut off. During each cycle, current flows only during necessary switching transitions rather than continuously, enabling high-frequency operation with reduced average power consumption compared to continuously conducting logic families.
Solution Approach 2:
The patent converts the typically harmful effect of parasitic capacitances and resistances into beneficial speed enhancement by operating in a regime where these effects dominate at high frequencies. The emitter-coupled topology with controlled current sources exploits parasitic effects to achieve faster switching at high frequencies while the periodic operation limits average power consumption.
Data Source
AI summary
Emitter-coupled logic circuits and systems that include such circuits are provided. Some emitter-coupled logic circuits include a plurality of fT-doubler circuits. Each fT-doubler circuit includes a plurality of transistors coupled to one another in an arrangement such that the plurality of transistors are configured to behave as a single enhanced transistor that has an effective unity current gain frequency that is higher than if a single transistor were used in its place. The fT-doubler circuits are configured to increase an operating frequency capability of the emitter-coupled logic circuit. Some emitter-coupled logic circuits include a plurality of cascode amplifier circuits. Each cascode amplifier circuit includes multiple transistors. An emitter of at least one first transistor of the plurality of transistors is coupled to a collector of at least one second transistor of the plurality of transistors Some emitter-coupled logic circuits may include both fT-doubler circuits and cascode amplifier circuits.