ECO Cell Layout With Tolerance Vias for Higher Density
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Solution Overview
Problem
The challenge in semiconductor device design is to reduce the size of standard cells to increase device density while maintaining alignment precision and reducing electrical resistance, as existing methods either compromise on alignment tolerance or increase the overall height of the standard cell.
Innovation Solution
The introduction of tolerance contacts and vias that extend beyond the underlying conductive structures, allowing for reduced metallization segment sizes and increased alignment tolerance, which in turn decreases the overall height of the standard cell and enhances semiconductor device density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of standard cells is reduced to increase device density, then device density is improved, but alignment precision deteriorates
Solution Approach 1:
The patent extends tolerance contacts and vias in the vertical dimension beyond the underlying conductive structures. This vertical extension creates an overlapping region that provides alignment tolerance without increasing the horizontal footprint of the standard cell, thus maintaining high device density while improving alignment precision.
Solution Approach 2:
The tolerance contact acts as an intermediary element between the upper and lower conductive structures. By extending beyond both structures and providing an overlapping region, it mediates the alignment relationship, allowing for reduced alignment precision requirements while maintaining electrical connectivity.
2Quantity of substance
If the size of standard cells is reduced to increase device density, then device density is improved, but alignment tolerance increases (worsens)
Solution Approach 1:
The patent utilizes the vertical dimension to extend tolerance contacts and vias beyond the underlying conductive structures. This creates an overlapping region that provides alignment tolerance in the horizontal plane without increasing the standard cell's horizontal dimensions, thereby maintaining high device density while accommodating larger alignment tolerance.
3Quantity of substance
If metallization segment sizes are reduced, then device density is improved, but electrical resistance increases
Solution Approach 1:
The patent implements a nested structure where the tolerance contact is positioned within the overlapping region of extended vias. This nesting allows the metallization segments to be minimized in size while the extended vias provide additional conductive path area, maintaining low electrical resistance despite reduced metallization segment sizes.
Solution Approach 2:
The patent compensates for reduced metallization segment area by extending conductive structures in the vertical dimension. The extended vias and tolerance contacts create additional conductive pathways vertically, maintaining electrical conductivity while reducing horizontal footprint for higher device density.
Data Source
AI summary
A method of manufacturing an ECO base cell includes forming first and second active areas on opposite sides of, and having corresponding long axes arranged parallel to, a first axis of symmetry; forming non-overlapping first, second and third conductive structures having long axes in a second direction perpendicular to the first direction and parallel to a second axis of symmetry, each of the first, second and third conductive structures to correspondingly overlap the first and second active areas, the first conductive structure being between the second and third conductive structures; removing material from central regions of the second and third conductive structures; and forming a fourth conductive structure being over the central regions of the second and third conductive structures and occupying an area which substantially overlaps a first segment of the first conductive structure and a first segment of one of the second and third conductive structures.