ECO Cone Pair Extraction for Semiconductor Circuit Engineering Change
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Solution Overview
Problem
Conventional Engineering Change Orders (ECOs) in semiconductor circuit design are manual and time-consuming, often resulting in excessive ECO logic due to the difficulty in locating modified elements within optimized circuits, leading to inefficient physical design changes and routing issues.
Innovation Solution
A method that automatically locates minimal ECO cone pairs by performing synthesis-with-optimization operations while preserving specified elements, using Fan-In Trace and Equivalent Check techniques to build logic cone data structures and identify non-equivalent cone pairs, thereby minimizing ECO logic and efficiently modifying post layout circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If manual ECO process is used to modify post layout circuit, then designers can directly apply changes to physical design, but the process becomes time-consuming and difficult due to manual location of elements
Solution Approach 1:
The system performs automatic ECO cone pair extraction by itself without requiring manual intervention. The computer automatically locates modified elements, extracts ECO cones, and identifies cone pairs, replacing the manual process of element location and ECO logic generation.
Solution Approach 2:
The manual mechanical process of element location and ECO analysis is replaced by an automated computer-based system that uses logic cone data structures and algorithmic extraction methods to perform the same function more efficiently.
2Device complexity
If logic optimization is applied during synthesis, then circuit is optimized, but modified elements become hidden or optimized away making them hard to locate
Solution Approach 1:
The system performs preliminary actions by building logic cone data structures before the optimization process obscures element relationships. By pre-establishing the cone structures that track element dependencies, the system can later locate modified elements even after optimization has been applied.
Solution Approach 2:
The logic cone data structure acts as an intermediary between the optimized circuit and the ECO modification process. It preserves the relationship information between elements that would otherwise be lost during optimization, enabling accurate location of modified elements.
3Reliability
If excessive ECO logic is generated due to difficulty in locating modified elements, then all possible elements are covered, but the ECO logic becomes larger than necessary and causes routing issues
Solution Approach 1:
The system extracts only the necessary ECO logic by identifying specific ECO cone pairs that contain the modified elements. Instead of taking out all possible logic, it selectively extracts minimal cones that are functionally relevant to the modification, reducing ECO logic size while maintaining reliability.
Solution Approach 2:
The ECO modification is applied locally to specific cone pairs rather than globally to the entire circuit. By identifying and modifying only the local regions containing changed elements, the system generates minimal ECO logic that maintains reliability without unnecessary complexity.
Data Source
AI summary
A method of engineering change to a semiconductor circuit includes: performing a first synthesis with optimization of a first HDL code to generate a first circuit; performing a first physical design of the first circuit to generate a post layout circuit; modifying the first HDL code to generate a second HDL code, and performing a second synthesis with optimization of the first and second HDL codes while forcibly preserving elements to generate a second circuit and a third circuit, respectively; performing an ECO cone-pair extraction operation of the second and third circuit to generate at least one ECO cone-pair; and obtaining an ECO logic and an element to be replaced according to the ECO cone-pair and the post layout circuit, and then replacing the element to be replaced in the post layout circuit with the ECO logic gate circuit, thereby modifying the post layout circuit into a post layout ECO circuit.