ECS Pulse Generator with Fixed-Delay Width Control for DRAM
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Solution Overview
Problem
The instability of the pulse width of the ECS pulse signal in different working scenarios leads to errors in the ECS mode of DRAM, affecting memory performance.
Innovation Solution
A pulse generator with a delay module and a latch module that stabilizes the pulse width of the ECS pulse signal by determining it based on a preset delay value, independent of the ECS command signal's pulse width, ensuring consistent performance across varying external frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the ECS command signal is generated by multi-purpose command or refresh instruction in different working scenarios, then the memory can operate in various modes, but the pulse width of the ECS pulse signal becomes unstable
Solution Approach 1:
The patent introduces an intermediary mechanism (delay circuit and latch circuit) between the ECS command signal and the output pulse signal. The delay circuit generates a delayed version of the command signal, and the latch circuit uses both the original and delayed signals to generate a standardized pulse output. This intermediary structure decouples the output pulse width from the variable input command signal width, maintaining stability across different operating modes.
Solution Approach 2:
The patent changes the parameter determination method from direct use of command signal pulse width to using a fixed delay value. By setting a predetermined delay time in the delay circuit, the output pulse width is determined by this fixed parameter rather than varying with the input signal characteristics, ensuring consistent pulse width regardless of operating mode.
2Adaptability or versatility
If the pulse width of ECS command signal varies greatly in different working scenarios, then the memory can adapt to different frequencies, but errors occur in the ECS mode
Solution Approach 1:
The latch circuit acts as an intermediary that filters out the variability of input signal parameters. It receives both the original ECS command signal and its delayed version, then generates a standardized output pulse regardless of the input pulse width variations. This intermediary structure ensures reliable ECS mode operation by eliminating the direct relationship between variable input width and output execution.
Solution Approach 2:
The delay circuit provides beforehand cushioning by pre-processing the command signal to create a time-shifted version. This delayed signal serves as a protective mechanism that ensures the output pulse width is always sufficient regardless of how short the input command signal may be, preventing errors by compensating for potential insufficient pulse widths in advance.
Data Source
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AI summary
A pulse generator, an Error Check and Scrub (ECS) circuit and a memory are provided. The pulse generator includes: a delay module configured to receive an ECS command signal, perform delay processing on the ECS command signal, and output a delay command signal, the delay between the ECS command signal and the delay command signal being a first preset value; and a latch module configured to receive the ECS command signal and the delay command signal, perform latch processing based on the ECS command signal and the delay command signal, and output an ECS pulse signal. The pulse width of the ECS command signal is provided with a plurality of values, and the pulse width of the ECS pulse signal is the first preset value.