ECS Pulse Generator with Fixed-Width Output for DRAM Reliability
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Solution Overview
Problem
The instability of the pulse width of the ECS pulse signal in different working scenarios leads to errors in the ECS mode, affecting the performance of Dynamic Random Access Memory (DRAM).
Innovation Solution
A pulse generator is designed with a delay circuit and a latch circuit to generate an ECS pulse signal with a stable pulse width. The delay circuit receives an ECS command signal, performs delay processing, and outputs a delay command signal, while the latch circuit processes the ECS command signal and the delay command signal to output the ECS pulse signal. The pulse width of the ECS pulse signal is fixed at a preset value, independent of the ECS command signal's pulse width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the pulse width of the ECS command signal varies in different working scenarios, then the pulse generator can adapt to different command types, but the pulse width of the ECS pulse signal becomes unstable, leading to errors in ECS mode
Solution Approach 1:
The patent introduces a delay circuit as an intermediary component between the ECS command signal input and the ECS pulse signal output. This delay circuit receives the ECS command signal, performs delay processing to generate a delay command signal, and uses the delay between the original command signal and the delayed signal to generate an ECS pulse signal with stable width. The delay circuit acts as a mediator that transforms variable-width input commands into fixed-width output pulses, resolving the contradiction between adaptability and reliability.
Solution Approach 2:
The patent changes the parameter of pulse width from variable (dependent on input command) to fixed (determined by delay value). By using a preset delay value in the delay circuit, the output ECS pulse signal width is determined by the delay parameter rather than the variable input command width. This parameter transformation ensures that regardless of the input command's pulse width, the output pulse maintains a stable, predetermined width, thereby improving reliability while maintaining adaptability.
2Device complexity
If the pulse width of the ECS command signal is directly used, then the circuit structure remains simple, but the pulse width of the ECS pulse signal varies greatly, causing errors in ECS mode
Solution Approach 1:
The delay circuit serves as an intermediary that adds minimal structural complexity while significantly improving reliability. By inserting this single functional block between the command signal input and pulse output, the system transforms unreliable variable-width pulses into reliable fixed-width pulses without requiring complex control logic or multiple circuit components.
Solution Approach 2:
The delay circuit automatically generates the appropriate pulse width based on its internal preset delay value, without requiring external control or adjustment. The circuit self-regulates the output pulse width to be exactly equal to the delay value, eliminating the need for complex external control mechanisms and maintaining circuit simplicity while ensuring operational accuracy.
Data Source
AI summary
A pulse generator, an Error Check and Scrub (ECS) circuit and a memory are provided. The pulse generator includes: a delay circuit configured to receive an ECS command signal, perform delay processing on the ECS command signal, and output a delay command signal, the delay between the ECS command signal and the delay command signal being a first preset value; and a latch circuit configured to receive the ECS command signal and the delay command signal, perform latch processing based on the ECS command signal and the delay command signal, and output an ECS pulse signal. The pulse width of the ECS command signal is provided with a plurality of values, and the pulse width of the ECS pulse signal is the first preset value.