ECU Memory Writing with Dual RAM Buffer Switching
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Solution Overview
Problem
The increasing amount of data to be written in the memory of electronic control units (ECUs) for vehicles necessitates a further reduction in the time required for the data writing process to improve production efficiency.
Innovation Solution
The control apparatus employs a method where data is transferred to two RAM areas, with a Direct Memory Access Controller (DMAC) managing the transfer and a CPU designating one area for initial data storage and switching to another area upon receiving a block transmission start request, allowing for parallel data processing and reduction in data transmission time by eliminating the need for position information and enabling efficient check value verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is transferred sequentially to a single buffer area before writing to nonvolatile memory, then data integrity is ensured, but the time required for the writing process increases
Solution Approach 1:
The buffer area is divided into two separate buffer areas (first buffer area and second buffer area). Data is transferred to one buffer area while simultaneously being written from the other buffer area to nonvolatile memory, enabling parallel operations and reducing total writing time while maintaining data integrity through the segmented buffer structure
Solution Approach 2:
The system alternates between two buffer areas, using one buffer area for data reception while the other is being written to memory. This preliminary preparation of alternate buffers allows seamless switching and parallel processing, reducing the overall time required for the writing process
2Quantity of substance
If the amount of data to be written increases, then more comprehensive control programs and calibration data can be stored, but the writing process time increases
Solution Approach 1:
The dual buffer area system enables continuous data writing operations by alternating between buffers. While one buffer is being filled with incoming data, the other buffer's data is being written to nonvolatile memory simultaneously, maintaining continuous productive action throughout the writing process
Solution Approach 2:
The system transitions from a single-dimensional sequential writing approach to a two-dimensional parallel approach by introducing a second buffer area. This allows data transfer and memory writing to occur in different dimensional spaces simultaneously, effectively doubling the throughput capability
Data Source
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AI summary
The control device comprises: a first storage unit; a second storage unit which has a faster I/O speed than the first storage unit and has a first and a second storage region; and a control unit which, with either the first or the second storage region as a transfer destination region, and transmits a verification value for the data block to the write device. If the verification value is proper, the write device transmits a block transmission commencement request to the control unit prior to transmission of the next data block. If the block transmission commencement request has been received, the control unit switches the transfer destination region to the other of the first or the second storage region, and causes the data blocks which were stored in the transfer destination region prior to the switch to be written to the first storage unit.