EDA Cell Placement Optimizing Timing via LDE Pattern-S Arrangement

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In advanced integrated circuit (IC) processes beyond 7 nm, the performance of standard cells is vulnerable to Layout Dependent Effects (LDE), leading to significant deviations in actual performance compared to recorded values due to interactions with neighboring cells, which current design automation tools struggle to accurately predict and optimize.

Innovation Solution

The method involves leveraging LDE by strategically placing functional and spare cells to form patterns such as pattern-S, where cells with different active region heights are arranged to enhance performance, and using EDA tools to optimize cell placement and routing, incorporating pattern-S timing information into standard cell libraries to improve timing performance without degrading other paths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If standard cells are placed in advanced IC processes beyond 7 nm, then device integration density is improved, but performance deviation due to LDE increases

Engineering Contradiction:
Improveintegration densityVSAvoidperformance deviation
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent applies local quality by differentiating cell placement strategies based on local layout conditions. Specifically, it identifies timing critical cells and applies specialized placement patterns (like pattern-S) to these specific locations rather than using uniform placement across the entire chip. This local differentiation allows the design to achieve high integration density overall while maintaining performance accuracy in critical regions by compensating for LDE effects through targeted placement adjustments.

Inventive Principle:
Principle #3Local quality

2Speed

If cell placement is optimized for timing performance, then timing critical path performance is improved, but other design paths may be degraded

Engineering Contradiction:
Improvetiming performanceVSAvoiddesign path stability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent implements partial action by selectively applying optimization patterns only to timing critical cells rather than all cells in the design. The methodology identifies which cells lie on timing critical paths and applies pattern-S placement specifically to these cells, while leaving non-critical cells with standard placement. This partial optimization approach improves timing performance where needed without introducing unnecessary complexity or potential degradation in other design paths.

Inventive Principle:
Principle #16Partial or excessive action

3Measurement precision

If LDE effects are compensated through pattern-S placement, then actual performance aligns with recorded values, but design complexity increases

Engineering Contradiction:
Improveperformance accuracyVSAvoidplacement complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-characterizing cells with pattern-S placement information before actual placement occurs. The methodology pre-identifies timing critical cells, pre-determines appropriate placement patterns for these cells, and pre-calculates the LDE compensation effects. This preliminary preparation allows the placement tool to efficiently implement LDE compensation without adding significant complexity during the actual placement process, as the complex decisions have already been made in advance.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12141516B2System and method for improving design performance through placement of functional and spare cells by leveraging LDE effect
Publication Date: 2024.11.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12141516B2 patent drawing
  • US12141516B2 patent drawing
  • US12141516B2 patent drawing

AI summary

Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect (LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design. According to some embodiments, conducting placement and optimization further includes: moving the at least one spare cells to locations to abut the at least one timing critical cells to form pattern-S for each of the at least one timing critical cells.