Electronic Circuit Scenario Compression for EDA Efficiency
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Solution Overview
Problem
The complexity and resource-intensive nature of analyzing numerous scenarios for electronic circuit design, particularly due to variations in operating conditions and modes, lead to impractical memory requirements and prolonged run times, with conventional methods either failing to provide significant improvements or compromising analysis quality.
Innovation Solution
A computer-implemented method that identifies a dominant scenario for each mode, modifies its timing nodes to cover violations from other scenarios, thereby reducing the number of scenarios needing analysis without ignoring any violations, by adjusting the required times of timing nodes based on differences in slack values scaled by arrival time ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of scenarios is reduced to decrease memory requirements and run time, then productivity is improved, but measurement precision deteriorates because violations from ignored scenarios may be missed
Solution Approach 1:
The patent merges multiple scenario analyses by identifying a winner scenario and integrating violations from other scenarios into it. This combines the coverage of multiple scenarios into a single modified winner scenario, reducing the number of separate analyses needed while maintaining comprehensive violation detection across all original scenarios
Solution Approach 2:
The patent creates a modified copy of the winner scenario that incorporates violations from other scenarios. Instead of analyzing each scenario separately, it generates a composite scenario that copies and integrates the critical violation information from multiple source scenarios, enabling single-scenario analysis with multi-scenario coverage
2Device complexity
If conventional methods ignore large number of scenarios to reduce analysis complexity, then device complexity is reduced, but reliability deteriorates because final analysis may not satisfy requirements from ignored scenarios
Solution Approach 1:
The patent extracts violations from scenarios that would otherwise be ignored and incorporates them into the winner scenario. This extraction process ensures that critical violation information is preserved and analyzed even when the original scenarios are not separately analyzed, maintaining reliability while reducing complexity
Solution Approach 2:
The patent performs preliminary identification and extraction of violations from all scenarios before the final analysis. By pre-processing the violation information and integrating it into the winner scenario, the method ensures that no critical violations are missed in the simplified analysis process
Data Source
AI summary
The number of scenarios analyzed for an electronic circuit is reduced to improve the processing time and resource requirements of electronic design automation processes. Each scenario is associated with a mode and a corner for the electronic circuit. Groups of scenarios corresponding to different corners for the same mode are identified. A winner scenario from each group is identified, for example, by selecting the dominant scenario from the group that covers the most number of violations in the group. The winner scenario is adjusted to account for violations of other scenarios of the group. The adjustment corresponding to a violation for a timing node from another scenario is performed by reducing the required time of the timing node in the winner scenario by a margin. The margin is determined based on timing information from the other scenario scaled to account for differences between the two scenarios.