EDA Dummy Tile Placement for IC Interconnect Signal Integrity
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Solution Overview
Problem
Existing integrated circuit design tools face challenges in placing dummy tiles, leading to increased parasitic capacitance and signal transmission delays, especially when interconnect lines operate at different voltage levels, which complicates noise characterization and reduces manufacturing yield.
Innovation Solution
An electronic design automation (EDA) tool that identifies interconnect lines at different voltage levels and applies specific criteria to determine where to insert dummy tiles, defining blockage areas and skipping long parallel runs to minimize parasitic capacitance and enhance signal integrity, while ensuring uniform pattern density for efficient chemical-mechanical polishing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy tiles are inserted to unify pattern density, then manufacturing yield is improved, but parasitic capacitance between interconnect lines increases
Solution Approach 1:
The patent applies different treatment to different regions by identifying interconnect lines at different voltage levels and defining blockage areas specifically between such lines. Dummy tiles are selectively placed only in regions that do not contain blockage areas, thereby achieving uniform pattern density while avoiding increased parasitic capacitance between lines at different voltage levels.
2Manufacturing precision
If dummy tiles are placed between interconnect lines at different voltage levels, then pattern density is unified, but signal integrity is degraded
Solution Approach 1:
The patent performs preliminary identification of interconnect lines at different voltage levels and defines blockage areas between them before the dummy tile placement process. This preliminary action ensures that dummy tiles are never placed in blockage areas, thereby preventing degradation of signal integrity while still achieving pattern density uniformity in non-blockage regions.
3Manufacturing precision
If existing tiling algorithms are used to place dummy tiles, then pattern density is improved, but design complexity increases due to noise characterization
Solution Approach 1:
The patent extracts and removes the problematic element by defining blockage areas between interconnect lines at different voltage levels, thereby excluding these regions from dummy tile placement. This extraction eliminates the source of noise issues and simplifies noise characterization, while dummy tiles are still placed in safe regions to achieve pattern density improvement.
Data Source
AI summary
An electronic design automation (EDA) tool for inserting dummy tiles between interconnect lines of an integrated circuit design includes a memory for storing the integrated circuit design and a processor in communication with the memory. The processor identifies those interconnect lines that are at different voltage levels, have a length greater than a predefined threshold length and a spacing less than a predefined threshold spacing, and inserts blockage areas between such interconnect lines. The processor skips the blockage areas and adds dummy tiles only between those interconnect lines that do not meet predetermined criteria.