EDA Verification Fix Guide Generation for IC Design Rule Violations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Electronic design automation (EDA) tools face challenges in efficiently handling verification errors or violations in IC design, as fixing one issue can introduce or induce other errors, and complex designs often violate multiple rules in various ways, making it cumbersome to detect and implement fixes without causing new violations.
Innovation Solution
A system and method that store fix information for each layer during verification, performing dimensional checking operations to create and propagate fix information, and generating fix guides based on the final fix information list to address design rule violations while minimizing new errors, using geometric shapes and design rules to intelligently determine and display fix guides for designers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If EDA tools provide comprehensive design rule checking, then verification accuracy is improved, but the complexity of handling and fixing violations increases
Solution Approach 1:
The patent segments verification violations into multiple categories (e.g., spacing violations, enclosure violations, width violations) and handles each type systematically through dedicated fix guide mechanisms. This segmentation allows the system to manage comprehensive verification accuracy while reducing the complexity of handling violations by breaking down complex multi-rule violations into manageable categories with specific resolution strategies.
2Ease of operation
If EDA tools provide detailed fix guides for each violation, then ease of fixing is improved, but the amount of information to process increases
Solution Approach 1:
The patent extracts essential fix information from complex verification results and presents only the critical details through visual fix guides. Instead of displaying all verification data, the system extracts and highlights only the necessary information (such as violation locations, required adjustments, and affected design rules) in an intuitive visual format, reducing information overload while maintaining ease of fixing.
Solution Approach 2:
The patent uses visual indicators and color coding in fix guides to convey different types of violations and their severities. By using color changes and visual markers, the system presents detailed fix information in an intuitive manner that reduces cognitive load and information processing requirements, making it easier for users to understand and resolve violations without being overwhelmed by text-heavy detailed information.
3Productivity
If EDA tools automatically propagate fix information through layers, then productivity is improved, but the risk of introducing new errors increases
Solution Approach 1:
The patent implements feedback mechanisms that allow users to review and validate propagated fix information before applying changes. The system provides feedback about potential conflicts and new violations that may arise from proposed fixes, enabling users to make informed decisions about whether to apply automated fixes or manually adjust the design. This feedback loop maintains productivity while mitigating the risk of introducing new errors through careful user validation.
Data Source
AI summary
Systems, apparatus and methods for handling verification violations are disclosed. In one aspect, a method stores a list of fix information in addition to geometric shapes for each layer during verification, such as design rule checking For each primitive operation step performed during verification, two tasks are performed. First, if the primitive operation is a dimensional checking operation (i.e., width, spacing or enclosure), then for each violation, the first task creates fix information containing violation edge pairs and adds the created fix information to the fix information list on the output layer. Second, for all operations and after the output shapes on the output layer are generated, a second task passes the fix information on input layers which overlap any output shape of the output layer to the output layer's fix information list. Finally, fix guides for the final violation results are generated and drawn based on the final fix information list.