Incremental Delay Annotation for EDA Netlist Optimization
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Solution Overview
Problem
In electronic design automation (EDA) tools, incremental changes to system designs require re-annotating entire designs, leading to significant additional time and impacting compile time, especially when only partial changes are made.
Innovation Solution
Identify impacted components and routing connections in a netlist due to incremental design changes, compute new delay information for these components, and reuse previously computed delays for unaffected components, while considering parasitic capacitive loading to reduce re-annotation efforts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If entire system design is re-annotated after incremental changes, then timing accuracy is maintained, but compile time increases significantly
Solution Approach 1:
The patent segments the delay annotation process by identifying and separating impacted components from unaffected components in the netlist. Only the impacted segments (components and routing connections affected by design changes) are re-annotated, while unaffected segments retain their previously computed delays. This segmentation approach maintains timing accuracy for changed portions while avoiding redundant computation for unchanged portions, thereby resolving the contradiction between timing precision and compile time.
Solution Approach 2:
The patent applies partial action by performing delay annotation only on the necessary subset of components that are actually impacted by design changes, rather than annotating the entire system design. The method identifies impacted components through netlist comparison and parasitic capacitance analysis, then applies delay annotation exclusively to these partial elements, eliminating wasted computational effort on unaffected components while preserving overall timing accuracy.
2Adaptability or versatility
If incremental changes are made to system design, then design flexibility is improved, but re-annotation effort increases
Solution Approach 1:
The patent extracts and isolates only the impacted components and routing connections from the full netlist after incremental design changes. By using netlist comparison techniques and parasitic capacitance loading analysis, the method extracts the minimal subset of elements that require re-annotation, separating them from the majority of unaffected components. This extraction process enables design flexibility through incremental changes while maintaining high re-annotation efficiency by processing only the necessary elements.
3Measurement precision
If parasitic capacitive loading is considered, then delay computation accuracy is improved, but computational complexity increases
Solution Approach 1:
The patent performs preliminary computation of parasitic capacitive loading for all routing connections before the incremental design changes occur. This preliminary parasitic capacitance information is stored and then used during incremental delay annotation to quickly determine which components are impacted by design changes. By performing this complex parasitic analysis in advance, the method achieves high delay computation accuracy for impacted components while reducing the computational complexity during the actual incremental re-annotation process.
Data Source
AI summary
A method for designing a system on a target device includes identifying components and routing connections impacted by incremental design changes made to a system design. New information is computed to annotate delays for the components and routing connections identified. Delays previously computed for components and routing connections are utilized to annotate delays for components and routing connections that have not been impacted by the changes made to the system design.