EDA Layout Editing With Wafer Contour Prediction for Hotspot Fixing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity of design rules and computational expense of lithography simulations hinder interactive design and hotspot fixing in IC manufacturing, leading to delays and reduced productivity.
Innovation Solution
Utilize machine-trained neural networks to predict manufactured wafer contours, enabling fast edit loops and interactive design by incorporating OPC/ILT effects, allowing for concurrent processing and GPU acceleration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If lithography simulation is performed to find hotspots, then manufacturing precision is improved, but productivity deteriorates due to computational expense
Solution Approach 1:
The patent creates a simplified computational model (digital twin) that copies the essential manufacturing process behavior from complex lithography simulations. This digital twin uses pre-computed lookup tables and simplified physics models to replicate hotspot detection capabilities without requiring full lithography simulation computational resources, enabling fast iterative design while maintaining manufacturing precision.
Solution Approach 2:
The patent performs preliminary computations by pre-calculating lithography simulation results for various design patterns and storing them in lookup tables before the actual design iteration begins. This pre-computation phase captures the complex manufacturing physics in advance, allowing the interactive design tool to query pre-computed results rather than performing full simulations during design iterations, thus improving productivity while maintaining manufacturing precision.
2Manufacturing precision
If design rules are made restrictive to accommodate all possibilities, then manufacturing precision is improved, but device complexity increases due to rule bloat
Solution Approach 1:
The patent implements context-aware design rules that adapt to local design patterns and neighboring structures. Instead of applying uniform restrictive rules across the entire chip, the system analyzes local geometry and manufacturing risk, applying relaxed rules where safe and restrictive rules only where needed. This local quality approach reduces overall rule complexity while maintaining manufacturing precision through targeted application of constraints.
Solution Approach 2:
The patent dynamically adjusts design rule parameters based on local design context, neighboring structures, and manufacturing process variations. Rather than using fixed conservative parameters for all designs, the system modifies rule parameters (such as spacing requirements, width constraints) according to actual local conditions and predicted manufacturing outcomes, reducing unnecessary rule bloat while maintaining compliance and precision.
Data Source
AI summary
A method for manufacturing-aware editing of circuit layouts driven by predictions regarding predicted manufactured wafer contours generated by a machine-trained network. The method allows for fast edit loops in interactive editing timeframes, in which the predicted manufactured wafer contours corresponding to design edits are presented within seconds of the edits themselves. In some embodiments, the wafer contours take mask OPC/ILT and lithography effects into account, as determined by the machine trained network.