Parallel EDA Locking via Partitioned Zone Slices
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Solution Overview
Problem
The increasing complexity of integrated circuit designs due to smaller feature sizes and larger data quantities leads to longer processing times for EDA tools, and existing parallel processing methods face challenges with data dependencies and high costs associated with integrating switchboxes, necessitating an improved approach for parallelization.
Innovation Solution
The implementation of efficient locking mechanisms at the layer purpose-pair and zone tree/slice levels to minimize blocking and data conflicts, allowing for effective parallel processing of IC layouts by using locks that correspond to specific purpose pairs or zone slices, reducing the granularity of locking and minimizing blocking between threads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If parallel processing is implemented for EDA tools, then processing speed is improved, but data conflicts and blocking between threads increase
Solution Approach 1:
The patent segments the IC layout into multiple partitions, with each partition processed by a separate thread. This spatial segmentation reduces data conflicts by isolating the data accessed by different threads to specific partitions, allowing parallel processing while minimizing interference between threads.
Solution Approach 2:
The patent implements fine-grained locking at the partition level rather than global locking, meaning each partition has its own lock. This local quality approach allows threads to access different partitions simultaneously without blocking each other, improving parallel processing efficiency while maintaining data consistency within each partition.
2Productivity
If fine-grained locking is implemented at partition level, then blocking between threads is reduced, but system complexity increases
Solution Approach 1:
The locking mechanism is segmented into partition-level locks rather than a single global lock. Each partition maintains its own lock state, which simplifies the locking logic by making it localized to specific data regions. Threads only need to acquire locks for the partitions they access, reducing overall system complexity compared to global locking while enabling better parallel processing.
3Adaptability or versatility
If IC designs use smaller feature sizes and more components, then circuit functionality is improved, but processing time for EDA tools increases
Solution Approach 1:
The patent divides the large-scale IC design into multiple smaller partitions that can be processed in parallel. This segmentation allows EDA tools to handle complex designs with more components and smaller feature sizes by distributing the processing workload across multiple threads, thereby reducing overall processing time while maintaining full design functionality.
Solution Approach 2:
The patent performs preliminary partitioning of the IC layout before parallel processing begins. This preliminary action organizes the design data into manageable partitions with defined boundaries, enabling subsequent parallel processing to proceed efficiently without data conflicts, thus reducing processing time for complex designs.
Data Source
AI summary
Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking.