EDA Tool Pitch Analysis for Integrated Circuit Design Rule Checks
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Solution Overview
Problem
In advanced semiconductor fabrication, existing electronic design automation (EDA) tools face challenges in accurately determining design rule violations, often leading to false alarms and manual re-checks, which are time-consuming and inefficient, especially when evaluating pitch violations in integrated circuit layouts under different voltage levels.
Innovation Solution
The implementation of a method within EDA tools to automatically analyze conductive lines in integrated devices, applying customized voltage levels to distinguish between true and false violations, thereby reducing the need for manual re-checks and streamlining the design rule check (DRC) process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing EDA tools are used to determine design rule violations, then the design rule check process can be performed, but false alarms occur leading to time-consuming manual re-checks
Solution Approach 1:
The system performs preliminary analysis by extracting pitch information from layout data before conducting design rule checks. This preliminary action includes identifying conductive lines, determining their pitches, and storing this information for later use, thereby preparing the data structure needed to avoid false alarms and reduce manual re-checks
Solution Approach 2:
The system implements feedback by comparing pitch information extracted from layout data with pitch information from device data. When violations are detected, the system provides feedback to distinguish between true violations and false alarms, allowing automated correction without manual intervention and improving the accuracy of subsequent design rule checks
2Reliability
If manual re-checks are performed to verify design rule violations, then accuracy can be improved, but productivity decreases due to time-consuming verification
Solution Approach 1:
The system performs self-service by automatically extracting pitch information, comparing it with device data, and determining whether violations are true or false. This self-service capability eliminates the need for manual verification while maintaining high accuracy, thereby improving productivity without sacrificing reliability
Solution Approach 2:
The system replaces manual mechanical verification processes with automated computational methods. By using algorithms to extract pitch information, compare data, and determine violations, the system substitutes human manual re-checks with automated electronic processing, significantly improving productivity while maintaining or enhancing accuracy
3Device complexity
If pitch information is not extracted and analyzed, then the design rule check process is simpler, but false alarms cannot be distinguished from true violations
Solution Approach 1:
The system segments the design rule check process into distinct stages: extracting pitch information from layout data, storing it in a database, comparing it with device data, and determining violations. This segmentation makes the complex process manageable and systematic, improving measurement precision without overwhelming complexity
Solution Approach 2:
The system introduces pitch information extraction and comparison as an intermediary step between layout data and design rule violation determination. This intermediary process provides the necessary information to distinguish true violations from false alarms, improving measurement precision while adding structured complexity that enhances rather than hinders the overall process
Data Source
AI summary
A method for forming an integrated device includes the following operations. A first circuit layout is provided. The first circuit layout includes a first device and a connecting portion. A first voltage level is applied to the first circuit layout. The first circuit layout is analyzed according to the first voltage level to determine if a failing signal occurs in the first circuit layout. The first device is analyzed when the failing signal occurs. It is determined, according to a second voltage level, whether a violation occurs in the first device. The first circuit layout is modified when a violation occurs.