EDA Power Domain Verification for IC Overstress Prevention
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Solution Overview
Problem
Conventional EDA tools lack an effective method to determine whether transistors in integrated circuits are coupled to the correct power supply, leading to potential overstress conditions that can damage gate oxides or cause hot carrier effects.
Innovation Solution
The development of EDA tools that verify whether individual blocks are connected to the correct power domain by analyzing the structural representation of integrated circuits, comparing supply voltages with operating voltages, and providing error messages to alert designers of adverse voltage relationships.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional EDA tools are used to arrange devices on integrated circuits, then designers have flexibility to make design changes quickly, but the tools cannot detect whether transistors are coupled to the correct power supply, leading to potential overstress conditions
Solution Approach 1:
The patent performs power domain verification during the design phase before manufacturing. The EDA tool analyzes the structural representation of the integrated circuit to identify blocks coupled to supply nodes, compares operating voltages with supply voltages, and detects adverse voltage relationships before the circuit is manufactured, preventing overstress conditions while maintaining design flexibility
Solution Approach 2:
The patent introduces an intermediary verification step between design and manufacturing. The EDA tool acts as an intermediary that analyzes the structural representation, identifies blocks and supply nodes, and provides feedback about voltage compatibility before the design is finalized for manufacturing, ensuring power supply coupling accuracy without restricting design freedom
2Reliability
If EDA tools verify power domain connections by analyzing structural representations and comparing voltages, then overstress conditions are prevented, but additional verification steps increase design complexity
Solution Approach 1:
The patent implements self-service verification where the EDA tool automatically analyzes the structural representation of the integrated circuit, identifies blocks and supply nodes, compares voltages, and generates reports without requiring manual intervention. The tool uses available design data to perform verification autonomously, reducing the burden on designers while ensuring reliability
Solution Approach 2:
The patent creates a universal verification method that can be applied to any integrated circuit design by analyzing structural representations. The EDA tool performs multiple functions including identifying blocks, identifying supply nodes, comparing voltages, and generating reports within a single integrated verification process, simplifying the overall verification complexity
Data Source
AI summary
Some aspects of this disclosure provide for electronic design automation (EDA) techniques that check whether individual blocks, such as transistors or other semiconductor devices, are connected to their correct power domains during design. In this way, the disclosed EDA techniques can limit or prevent overstress conditions applied to blocks and help to improve reliability of integrated circuits, when manufactured.