EDA Router for Double Patterning Lithography Conflict Resolution
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Solution Overview
Problem
Current semiconductor fabrication methods, such as double exposure techniques, face challenges in automating the decomposition process for pattern formation, particularly at nanometer scales, leading to issues like native conflicts and increased die area due to close feature spacing, which are not efficiently addressed by existing double dipole lithography (DDL) and double patterning technology (DPT).
Innovation Solution
A method and system that utilize an electronic design automation (EDA) tool with a router to identify one-dimensional routing paths and select two-dimensional routing patterns to connect cells in an integrated circuit layout, avoiding computationally intensive lithography engine interactions and allowing for high-resolution pattern formation without increasing line spacing, using a predetermined set of DDL/DPT friendly design rules and patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If double exposure methods are used to continue using fabrication equipment for larger technology nodes, then existing lithographic tools can be utilized, but the decomposition process becomes computationally intensive and complex
Solution Approach 1:
The patent segments the decomposition process into distinct phases: identifying conflicts between adjacent patterns, categorizing conflict types, and applying specific resolution rules. This segmentation transforms the complex computational problem into manageable steps that can be automated more efficiently
Solution Approach 2:
The patent introduces an intermediary conflict detection and resolution system that acts between the pattern design and the lithography process. This intermediary automatically identifies and resolves conflicts before fabrication, reducing the computational burden on the overall decomposition process
2Area of stationary object
If double patterning technology is used to reduce overall IC layout, then greater reduction in layout is achieved compared to DDL, but the process becomes more computationally intensive
Solution Approach 1:
The patent performs preliminary conflict detection and resolution before the main decomposition process. By pre-identifying and pre-resolving conflicts between adjacent patterns, the actual decomposition runs faster and more efficiently, maintaining the layout reduction benefits of DPT without the computational overhead
3Manufacturing precision
If spacing is increased between devices to address native conflicts, then high resolution exposure can be achieved, but the die area increases
Solution Approach 1:
The patent changes the parameters of the decomposition process by introducing conflict-type categorization and specific resolution rules. Instead of uniformly increasing spacing, the system selectively adjusts spacing only where conflicts exist, maintaining high resolution exposure while minimizing die area impact
4Reliability
If manual or semi-automated decomposition methods are used, then design control is maintained, but the process time and complexity increase
Solution Approach 1:
The patent implements a self-service decomposition system that automatically detects conflicts, categorizes them, and applies resolution rules without manual intervention. This automation maintains design control through rule-based decision making while dramatically reducing the time required for the decomposition process
Data Source
AI summary
A method includes receiving an identification of a plurality of cells to be included in an integrated circuit (IC) layout, including a list of pairs of cells within the plurality of cells to be connected to each other. First routing paths are identified, to connect a maximum number of the pairs of cells using one-dimensional (1-D) routing between cells within those pairs of cells. Second routing paths are selected from a predetermined set of two-dimensional (2-D) routing patterns to connect any of the pairs of cells which cannot be connected by 1-D routing. The first and second routing paths are output to a machine readable storage medium to be read by a control system for controlling a semiconductor fabrication process to fabricate the IC.