Automated Safety Verification in EDA Circuit Design

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Solution Overview

Problem

The manual process of designing and verifying safety-critical electronic circuits for applications like automotive and medical devices lacks standardization and automation, making it inefficient and prone to errors.

Innovation Solution

Integration of functional safety (FS) data into the electronic design automation (EDA) process flow for automated design and verification, including failure mode, effect, and diagnostic analysis (FMEDA) and dependent failure analysis (DFA), to ensure compliance with safety criteria through automated design updates and verification.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If manual processes are used for designing and verifying safety-critical electronic circuits, then flexibility and adaptability are maintained, but efficiency is reduced and error-prone operations occur

Engineering Contradiction:
Improvedesign and verification efficiencyVSAvoiderror reduction in safety-critical design
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system enables automated self-verification of safety criteria through integrated EDA tools that automatically check design compliance with safety standards, reducing reliance on manual verification processes and minimizing human error in safety-critical circuit design

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system implements automated feedback loops where verification results are continuously fed back into the design process, allowing real-time detection and correction of safety compliance issues during the design phase rather than through manual post-verification

Inventive Principle:
Principle #23Feedback

2Reliability

If manual verification processes are used, then comprehensive safety analysis can be performed, but the process is inefficient and time-consuming

Engineering Contradiction:
Improvesafety criteria complianceVSAvoidverification time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Safety verification checks are performed preliminarily during the design phase itself rather than as a separate post-design process, allowing safety compliance to be verified concurrently with design development and eliminating time loss from sequential manual verification

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system merges safety verification functions with standard EDA design tools into a unified automated process, combining design and verification operations that were previously separate manual processes into an integrated automated workflow

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If automated EDA processes are implemented, then design speed increases, but integration of safety criteria becomes complex

Engineering Contradiction:
Improvecircuit design speedVSAvoidsafety data integration complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system implements universal safety verification modules that can be applied across different EDA tool types and design stages, providing multi-functional safety checks that work with various design formats and reducing the complexity of integrating safety criteria across different tools

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10643011B1Automatic design and verification of safety critical electronic systems
Publication Date: 2020.05.05 CADENCE DESIGN SYST INC
  • US10643011B1 patent drawing
  • US10643011B1 patent drawing
  • US10643011B1 patent drawing

AI summary

Devices, methods, computer readable media, and other embodiments are described for design and verification of safety critical electronic systems. Some embodiments integrate functional safety (FS) data with circuit design data for use in electronic design automation (EDA) operations. One embodiment involves a device accessing FS and circuit design data; automatically analyzing register transfer level (RTL) design data using the FS data to perform one or more FS quality checks; and placing and routing the circuit design using the RTL design data and the set of FS data to perform FS-aware placement and routing. In some embodiments, failure modes and associated safety mechanisms to improve safety metrics associated with failure modes are automatically added to the circuit design during EDA operations. In other embodiments, additional FS-aware operations are performed. In some embodiments, the FS data is structured as a single Unified Safety Format (USF) file.