EDA Timing Analysis via Extended Partition Logic
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Solution Overview
Problem
Existing EDA tools face inefficiencies in timing analysis and optimization of integrated circuit designs due to the need to consider the entirety of the circuit, leading to increased processing time and potential unintended timing issues when optimizing discrete portions without accounting for external effects.
Innovation Solution
The approach involves expanding partitions in EDA tools to include external design portions affected by or affecting the analyzed partitions, allowing for logical consideration during timing optimization and analysis, thereby identifying unintended problems earlier and improving efficiency and system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the entire circuit design is analyzed for timing optimization, then timing accuracy is improved, but processing time and computational resources increase significantly
Solution Approach 1:
The patent divides the entire circuit design into multiple partitions, allowing timing analysis to be performed on discrete portions rather than the complete design. This segmentation enables parallel processing and reduces the computational burden on each analysis pass, thereby decreasing overall processing time while maintaining timing accuracy through iterative refinement across partitions.
Solution Approach 2:
The patent performs timing analysis on selected partitions rather than the entire design in each iteration. By focusing computational resources on specific regions of interest and using heuristics to identify critical partitions, the method achieves sufficient timing accuracy without the excessive computational cost of analyzing every component of the design.
2Productivity
If discrete portions of the circuit are optimized in isolation, then processing efficiency is improved, but unintended timing issues arise from external effects
Solution Approach 1:
The patent implements feedback mechanisms where timing analysis results from one partition are used to update and refine the analysis of other partitions. The system iteratively exchanges information between partitions, allowing optimizations in discrete portions to be validated against their impact on the overall design, thereby maintaining timing reliability while preserving processing efficiency.
Solution Approach 2:
The patent merges the results of timing analysis from multiple discrete partitions to form a comprehensive view of the entire circuit's timing behavior. By combining partition-level optimizations and validating them against global timing constraints, the method ensures that local optimizations do not create unintended timing issues elsewhere in the design.
3Area of stationary object
If more circuit elements are placed within the same chip area, then chip utilization is improved, but the number of timing problems increases
Solution Approach 1:
The patent segments densely packed circuit elements into manageable partitions, allowing timing analysis to scale with chip complexity. By organizing the increased number of circuit elements into discrete, analyzable units, the method maintains processing feasibility even as chip area utilization increases and the number of timing constraints grows.
Solution Approach 2:
The patent employs dynamic partitioning strategies that adapt to the density and complexity of circuit elements within the chip area. As more elements are placed on the chip, the system dynamically adjusts partition boundaries and analysis depth, focusing computational resources on regions with the most critical timing constraints while maintaining overall timing accuracy.
Data Source
AI summary
Operations are performed in EDA tools that operate upon partitions or discrete portions of an electronic design, in which the partitions or discrete portions of the design are expanded to account for effects to/from other areas in the design. Identification is made of the portions of the design that are external to the partitions, and depending upon the type of expected effects, would then be considered during optimization and analysis of the partitions. This is implemented by logically expanding the partition to include consideration of the external portions during timing optimization and analysis. By considering an expanded partition for timing optimization and analysis, it is possible to identify unintended problems caused by the timing optimization at an earlier stage of the design process.