EDA Tool Polygon Stitching for Multi-Patterning Parasitic Uncertainty
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Solution Overview
Problem
In semiconductor fabrication, multi-patterning methods introduce uncertainty in parasitic capacitances due to varying trench depths and mask misalignments, leading to discrepancies between simulation and actual IC performance, especially in high-precision and high-speed circuits.
Innovation Solution
The method involves dividing polygons into segments using multiple photomasks and inserting stitches to ensure consistent parasitic capacitance predictions across different mask alignments, allowing for more accurate simulation and design without excessive design margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multi-patterning methods are used to achieve smaller feature sizes, then manufacturing precision is improved, but reliability deteriorates due to parasitic capacitance uncertainty
Solution Approach 1:
The patent segments each circuit pattern into multiple parts by inserting stitches, where each part is assigned to a different photomask. This segmentation ensures that adjacent parts formed by different masks have different trench depths, creating a compensating effect that reduces overall parasitic capacitance uncertainty while maintaining the ability to form sub-minimum-separation patterns.
2Manufacturing precision
If multiple photomasks are used for patterning, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent divides patterns into segments assigned to different masks, which systematically manages the complexity of multi-mask processes. By inserting stitches at specific locations and assigning adjacent segments to different masks, the method creates a structured approach that reduces sensitivity to mask misalignment while achieving sub-minimum-separation pitch.
Solution Approach 2:
The patent applies different trench depths locally at different segments of the circuit patterns. By varying the trench depth characteristics in different local regions (corresponding to different mask assignments), the method creates compensating parasitic effects that reduce overall uncertainty without requiring uniform changes across the entire structure.
Data Source
AI summary
A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least N−1 stitches are inserted in each polygon within that set to divide each polygon into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other. Data representing assignment of each of the parts in each set to respective photomasks are stored in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks.