EDA Waveform Data Analysis for Partial Circuit Simulation
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Solution Overview
Problem
Traditional methods for debugging circuit designs using waveform data are costly and time-consuming, leading to bottlenecks in the design verification process due to the need for full simulations and manual adjustments.
Innovation Solution
The approach facilitates fast simulation cycles by allowing users to modify and debug circuit designs through a graphical user interface, where only affected portions of the design are resimulated, with previous results reused, and previewing changes before full simulation, enabling efficient RTL data updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full simulation is performed to debug circuit design, then debugging accuracy is improved, but turnaround time increases
Solution Approach 1:
The patent segments the circuit design into modular components (RTL modules, instantiated modules) that can be independently simulated and debugged. This allows the debugging system to focus only on relevant segments rather than performing full-circuit simulation, thereby maintaining debugging accuracy while reducing turnaround time through selective re-simulation of modified modules.
Solution Approach 2:
The system performs preliminary simulation to generate initial waveform data before design modifications are made. When changes are introduced, the system compares new waveform data with the pre-generated baseline data to quickly identify discrepancies. This preliminary action eliminates the need for complete re-simulation, achieving fast debugging feedback while maintaining accuracy.
2Adaptability or versatility
If manual changes are made to circuit design, then design flexibility is improved, but productivity decreases
Solution Approach 1:
The patent implements an automated feedback mechanism that monitors waveform data changes after manual design modifications. The system automatically compares pre-modification and post-modification waveform data, identifies discrepancies, and guides the designer on what changed. This feedback loop maintains design flexibility while improving productivity by eliminating manual analysis and providing automated debugging guidance.
Solution Approach 2:
The debugging system performs self-service by automatically detecting and reporting waveform discrepancies without requiring manual intervention. The system autonomously identifies which signals changed due to design modifications and presents this information to the designer, reducing the time and effort required for manual debugging while preserving design flexibility.
3Reliability
If complete resimulation is performed after design modification, then verification completeness is improved, but time consumption increases
Solution Approach 1:
The patent extracts and reuses waveform data from portions of the circuit design that were not modified. Instead of performing complete resimulation, the system identifies unchanged modules and retrieves their pre-existing waveform data, combining it with newly simulated data from modified sections. This extraction approach maintains verification completeness while dramatically reducing resimulation time.
Solution Approach 2:
The system discards the need to re-simulate unchanged portions of the circuit design and recovers their waveform data from previous simulation runs. By identifying which parts of the design remain unchanged and reusing their simulation results, the system maintains complete verification coverage while avoiding redundant time-consuming simulations.
Data Source
AI summary
Various embodiments provide for analyzing (e.g., debugging) waveform data generated for a simulated circuit design, which can be used as part of electronic design automation (EDA). For example, where a user modifies a circuit design in a manner that impacts a next simulation run performed on the circuit design, various embodiments perform the next simulation run only on one or more portions of the circuit design affected by the user's modifications, while the results/simulated values for the rest of the circuit design are kept or reused.