On-Chip EDAC SDRAM Architecture for Radiation-Hardened Memory
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Solution Overview
Problem
Commercial Off-The-Shelf (COTS) Synchronous Dynamic Random Access Memory (SDRAM) devices face reliability and performance issues in radiation environments due to effects like Total Ionizing Dose, Single-Event Upset, and Single-Event Latchup, which current systems fail to adequately address, leading to data retention failures and system errors.
Innovation Solution
A radiation-hardened SDRAM device is developed using Static Random Access Memory (SRAM) cells with Error Detection And Correction (EDAC) logic, implemented on-chip in each memory bank, which checks and generates Error Correction Codes during read and write bursts, and utilizes a second column multiplexer to select accessed bytes, enhancing radiation tolerance and error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If COTS SDRAM is used in radiation environments, then cost and ease of manufacture are improved, but reliability deteriorates due to radiation effects
Solution Approach 1:
The patent segments the memory array into multiple independently decodable banks, where each bank can be individually accessed and error-corrected. This segmentation allows the system to maintain high reliability in radiation environments by isolating radiation-induced errors to specific banks while preserving functionality in other banks, thus resolving the contradiction between using commercial components and ensuring reliability.
Solution Approach 2:
The patent changes the operational parameters by implementing asynchronous clocking schemes and adjustable timing parameters that optimize performance under radiation conditions. The memory device allows dynamic adjustment of timing parameters to compensate for radiation-induced delays, maintaining reliability while using commercial SDRAM components.
2Device complexity
If DRAM cells are used, then device complexity is reduced, but reliability deteriorates due to leakage current increase with TID radiation
Solution Approach 1:
The patent introduces an intermediary error correction and detection layer between the physical memory cells and the data access interface. This intermediary EDAC system monitors and corrects radiation-induced errors, acting as a mediator that preserves data retention reliability without requiring changes to the fundamental DRAM cell structure, thus maintaining low device complexity while improving reliability.
Solution Approach 2:
The patent implements a composite memory architecture that combines DRAM cells with redundant storage elements and error correction codes. This composite structure uses both volatile DRAM for primary storage and additional redundancy mechanisms for error protection, creating a hybrid system that maintains the simplicity of DRAM while adding radiation hardness through composite design.
3Duration of action of stationary object
If elevated voltage is used to maximize charge storage, then data retention is improved, but susceptibility to single-event gate rupture and latchup increases
Solution Approach 1:
The patent implements dynamic voltage adjustment where the Word Line voltage is adaptively controlled based on operational conditions and radiation environment. The system dynamically optimizes the voltage level to achieve sufficient data retention while minimizing the voltage-induced susceptibility to single-event gate rupture and latchup, resolving the contradiction between retention time and radiation susceptibility.
Solution Approach 2:
The patent changes the voltage parameter by implementing adjustable Word Line voltage levels that can be optimized for different operational modes. The system can lower the voltage during conditions where radiation susceptibility is a concern while maintaining adequate charge storage through compensating mechanisms, thus resolving the contradiction between data retention time and susceptibility to radiation effects.
4Duration of action of stationary object
If periodic refresh is implemented, then data retention is maintained, but active power consumption increases
Solution Approach 1:
The patent implements a self-service error correction mechanism where the memory system automatically detects and corrects errors using built-in redundancy and EDAC logic without requiring external intervention or frequent refresh operations. The system uses idle periods and existing memory operations to perform self-diagnosis and correction, reducing the need for periodic refresh cycles and thereby lowering active power consumption while maintaining data retention.
Data Source
AI summary
A method for radiation hardening synchronous Dynamic Random Access Memory (DRAM), where Error Detection And Correction (EDAC) is implemented on-chip. Each bank includes a plurality of interleaved single chip Static Random Access Memory (SRAM) cells with bit registers configured to interface with the interleaved SRAM cells. A first column multiplexer (MUX) configured to select which bit register is accessed. A second column multiplexer is configured to select an accessed byte with the WRITE burst or a READ burst from the selected bit registers of the first column multiplexer. EDAC logic is configured to check Error Correction Code (ECC) during a READ burst and generate ECC during an WRITE burst for SRAM writeback during a PRECHARGE command.