Overwriting EDC Field for Low-Complexity Packet Latency Measurement

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Solution Overview

Problem

Existing methods for measuring traversal latency in network elements require significant storage space and complex logic, making them inefficient in terms of chip area and power consumption.

Innovation Solution

A network element that overwrites part of the Error Detection Code (EDC) field in a packet with a timestamp to estimate traversal latency, using existing processing paths and reducing storage needs, and calculates latency by determining the difference between arrival and departure timestamps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional methods are used to measure traversal latency by storing complete packet descriptors, then measurement accuracy is maintained, but chip area and storage requirements increase significantly

Engineering Contradiction:
Improvelatency measurement accuracyVSAvoidchip area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent extracts only the essential timestamp information from the complete packet descriptor, storing only the input timestamp in the EDC field rather than the entire descriptor. This extraction approach maintains the necessary measurement capability while dramatically reducing the storage footprint required in the chip.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies local quality by selectively modifying only the EDC field to store the timestamp, while leaving the rest of the packet structure unchanged. This localized modification approach allows latency measurement functionality to be added without affecting or expanding the overall packet processing infrastructure.

Inventive Principle:
Principle #3Local quality

2Measurement precision

If complete packet descriptors are stored for latency measurement, then accurate latency calculation is achieved, but power consumption increases

Engineering Contradiction:
Improvelatency measurement accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by stationary object

Solution Approach 1:

The patent extracts only the essential timestamp information from the complete packet descriptor, storing only the input timestamp in the EDC field rather than the entire descriptor. This extraction approach maintains the necessary measurement capability while dramatically reducing the storage footprint required in the chip.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses the EDC field as a temporary, disposable storage location for the timestamp, which is overwritten with a new timestamp for each packet. This disposable use of existing field space eliminates the need for permanent timestamp storage structures, reducing both area and power requirements.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Device complexity

If dedicated timestamp storage fields are added to packets, then latency measurement is simplified, but packet structure complexity and storage requirements increase

Engineering Contradiction:
Improvemeasurement logic complexityVSAvoidstorage space
Core Design Contradiction:
Device complexityVSQuantity of substance

Solution Approach 1:

The patent makes the EDC field multi-functional by using it both for its original error detection purpose and for storing the input timestamp. This universal use of existing field space eliminates the need for dedicated timestamp storage, maintaining measurement functionality while avoiding additional storage requirements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent discards the original EDC value and recovers the EDC field for timestamp storage. The timestamp is temporarily stored in this recovered space during the measurement process, demonstrating how existing resources can be repurposed to achieve new functionality without additional overhead.

Inventive Principle:
Principle #34Discarding and recovering

Data Source

PatentUS10237156B2Low-complexity measurement of packet traversal time in network element
Publication Date: 2019.03.19 MELLANOX TECHNOLOGIES LTD(IL)
  • US10237156B2 patent drawing
  • US10237156B2 patent drawing
  • US10237156B2 patent drawing

AI summary

A network element includes multiple interfaces and circuitry. The interfaces are configured to connect to a communication system. The circuitry is configured to receive via an ingress interface a packet that includes an Error Detection Code (EDC) field including an input EDC value, to determine an input timestamp indicative of a time-of-arrival of the received packet at the network element, and overwrite at least part of the input EDC value in the EDC field of the packet with the input timestamp, to estimate for the packet a traversal latency between reception at the ingress interface and transmission via a selected egress interface, based at least on the input timestamp, and to produce a deliverable version of the packet by writing an output EDC value to the EDC field, and send the deliverable version of the packet via the selected egress interface.