EDDS Interface Embeds Control Signals Into Data Lines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional display systems face challenges in high-speed operations due to signal skewing and difficulty in adjusting timing parameters, leading to increased manufacturing costs and reduced yield, as they require multiple signal lines and complex interfaces for data, control, and clock signal transmission.
Innovation Solution
The implementation of an EDDS interface that embeds data, control, and clock signals into differential data lines, allowing for point-to-point transmission and decoding, eliminating the need for extra signal lines and simplifying the circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple separate signal lines are used for data, control, and clock signals, then signal transmission can be achieved, but signal skewing increases and timing parameter adjustment becomes difficult
Solution Approach 1:
The patent combines multiple separate signal lines (data lines, control lines, clock lines) into a single integrated signal line that transmits all signals multiplexed together. This merging approach eliminates the skewing issues between separate lines while reducing overall circuit complexity and the number of required connections.
Solution Approach 2:
The patent creates a universal signal line that performs multiple functions simultaneously - transmitting data signals, control signals, and clock signals through the same physical medium. This multi-functional approach replaces the traditional separate dedicated lines for each signal type, simplifying the interface while maintaining full functionality.
2Reliability
If separate signal lines are used for clock and data signals, then signal transmission is possible, but the number of pins increases and manufacturing cost increases
Solution Approach 1:
The patent merges clock signal transmission and data signal transmission into a single integrated line, eliminating the need for separate clock lines and reducing the total pin count. This directly reduces manufacturing complexity and cost while maintaining reliable signal transmission through the multiplexed approach.
3Productivity
If multiple signal lines are used for high-resolution display, then data transmission capacity is sufficient, but trace delay variation increases and timing adjustment becomes more difficult
Solution Approach 1:
The patent combines multiple signal transmissions into a single line, eliminating the varying trace delays that occur between multiple separate lines on large PCBs. By having all signals travel through the same physical path, timing synchronization is automatically maintained while still achieving the required data transmission capacity through multiplexing.
Data Source
AI summary
A display system includes a display panel, a timing controller, a plurality of source drivers and an EDDS interface. The control signals, the clock signals and the setting signals generated by the timing controller are embedded as protocols into the data signals. The embedded signals are then transmitted from the timing controller to each source driver via a corresponding pair of differential data lines of the EDDS interface. The decoders of the source drivers can then decode the embedded signals for generating corresponding driving signals for the display panel.